86 lines
2.1 KiB
ArmAsm
86 lines
2.1 KiB
ArmAsm
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// Shifts, division and multiply-accumulate, byte-parity-checked against
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// go tool asm: the immediate shift aliases (SBFM/UBFM, ROR via EXTR), the
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// register two-source forms (LSLV/LSRV/ASRV/RORV), SDIV/UDIV and the
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// four-operand MADD/MSUB. Every function body is padded to a whole number
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// of 16 bytes so the toolchain's object adds no trailing alignment.
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#include "textflag.h"
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// shiftimm exercises the immediate shift aliases in both widths.
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TEXT ·shiftimm(SB), NOSPLIT, $0-48
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MOVD x+0(FP), R0
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LSL $4, R0, R1
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LSR $8, R0, R2
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ASR $4, R0, R3
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ROR $12, R0, R4
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LSLW $4, R0, R5
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LSRW $8, R0, R6
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ASRW $4, R0, R7
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RORW $12, R0, R8
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MOVD R1, r1+0(FP)
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MOVD R2, r2+8(FP)
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MOVD R3, r3+16(FP)
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MOVD R4, r4+24(FP)
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MOVW R5, r5+32(FP)
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MOVW R6, r6+40(FP)
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RET
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// shiftreg exercises the register shift forms in both widths: the count
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// comes from a register, encoding as LSLV/LSRV/ASRV/RORV.
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TEXT ·shiftreg(SB), NOSPLIT, $0-40
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MOVD x+0(FP), R0
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MOVD c+8(FP), R20
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LSL R20, R0, R1
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LSR R20, R0, R2
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ASR R20, R0, R3
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ROR R20, R0, R4
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LSLW R20, R0, R5
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LSRW R20, R0, R6
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ASRW R20, R0, R7
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RORW R20, R0, R8
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MOVD R1, r1+0(FP)
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MOVD R2, r2+8(FP)
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MOVD R3, r3+16(FP)
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MOVD R4, r4+24(FP)
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MOVW R5, r5+32(FP)
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RET
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// shift2op exercises the two-operand spellings, which fold to Rn = Rd.
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TEXT ·shift2op(SB), NOSPLIT, $0-24
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MOVD x+0(FP), R1
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MOVD c+8(FP), R20
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LSL $4, R1
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LSR R20, R1
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LSL $12, R2
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ROR $8, R2
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LSLW $4, R3
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RORW $8, R3
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MOVD R1, r1+0(FP)
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MOVD R2, r2+8(FP)
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MOVD R3, r3+16(FP)
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RET
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// divmul exercises SDIV/UDIV in both widths and the four-operand
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// MADD/MSUB, whose accumulate register is the second operand (Rm, Ra, Rn,
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// Rd) and rides bits 14:10.
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TEXT ·divmul(SB), NOSPLIT, $0-40
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MOVD x+0(FP), R0
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MOVD y+8(FP), R1
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SDIV R1, R0, R2
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UDIV R1, R0, R3
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SDIVW R1, R0, R4
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UDIVW R1, R0, R5
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MADD R1, R0, R2, R6
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MSUB R1, R0, R2, R7
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MADDW R1, R0, R4, R8
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MSUBW R1, R0, R4, R9
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MOVD R2, r2+0(FP)
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MOVD R3, r3+8(FP)
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MOVD R6, r6+16(FP)
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MOVD R7, r7+24(FP)
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MOVD R8, r8+32(FP)
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RET
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