gasm-sdk/asm/testdata/seeds/riscv64/rvv.s

// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
// SPDX-License-Identifier: BSD-3-Clause

// Seed corpus for FuzzAssembleRISCV64: the RVV surface.  The configuration
// setters, the load/store families with their segment and fault-only-first
// variants, the arithmetic operand classes (VV/VX/VI, the masks, the
// merge and carry forms, the reductions and the whole-register moves).

#include "textflag.h"

TEXT ·config(SB), NOSPLIT, $0
	VSETVLI  X5, E8, M8, TA, MA, X6
	VSETVLI  X5, E8, M1, TU, MU, X6
	VSETVLI  $15, E32, M1, TA, MA, X12
	VSETVLI  $31, E64, M2, TU, MU, X12
	VSETIVLI $0, E16, M4, TA, MA, X0
	VSETIVLI $4, E32, M1, TA, MA, X0
	VSETIVLI $31, E8, M8, TU, MU, X15
	RET

TEXT ·loads(SB), NOSPLIT, $0
	VLE8V     (X10), V8
	VLE16V    (X10), V8
	VLE32V    (X10), V8
	VLE64V    (X11), V16
	VSE8V     V8, (X10)
	VSE16V    V8, (X10)
	VSE32V    V15, (X11)
	VSE64V    V24, (X10)
	VLSE8V    (X14), X9, V0
	VLSE32V   (X14), X5, V4
	VSSE64V   V4, X7, (X14)
	VLUXEI8V  (X10), V20, V4
	VLOXEI32V (X10), V20, V4
	VSUXEI64V V4, V20, (X10)
	VSOXEI16V V4, V20, (X10)
	VLE8FFV   (X10), V8
	RET

TEXT ·segments(SB), NOSPLIT, $0
	VLSEG2E8V     (X14), V0
	VLSEG4E32V    (X14), V0
	VLSEG8E64V    (X14), V4
	VSSEG2E32V    V0, (X14)
	VSSEG8E8V     V4, (X14)
	VLSSEG4E32V   (X14), X0, V0
	VLSSEG8E32V   (X10), X0, V4
	VLUXSEG2EI32V (X10), V20, V4
	VLOXSEG4EI64V (X10), V20, V4
	VSUXSEG2EI8V  V4, V20, (X10)
	VLSEG4E8FFV   (X14), V0
	RET

TEXT ·wholeReg(SB), NOSPLIT, $0
	VL1RV    (X10), V8
	VL2RV    (X10), V16
	VL4RV    (X10), V0
	VL8RV    (X10), V0
	VS1RV    V8, (X10)
	VS2RV    V16, (X10)
	VS4RV    V0, (X10)
	VS8RV    V0, (X10)
	VL1RE8V  (X10), V8
	VL2RE16V (X10), V16
	VL4RE32V (X10), V0
	VL8RE64V (X10), V0
	VL2RE64V (X10), V16
	VLMV     (X10), V0
	VSMV     V0, (X10)
	RET

TEXT ·arith(SB), NOSPLIT, $0
	VADDVV  V1, V2, V3
	VADDVV  V1, V2, V0, V3
	VADDVX  X10, V2, V0, V3
	VADDVI  $15, V2, V0, V3
	VADDVI  $-16, V2, V0, V3
	VADDVI  $0, V2, V3
	VSUBVV  V1, V2, V0, V3
	VSUBVX  X10, V2, V3
	VRSUBVX X10, V2, V0, V3
	VRSUBVI $15, V2, V0, V3
	VANDVI  $-1, V2, V3
	VORVI   $15, V2, V3
	VORVI   $-16, V2, V3
	VXORVI  $0, V2, V3
	VNEGV   V2, V0, V3
	VNOTV   V2, V3
	VIDV    V12
	VFMVVF  F10, V14
	VMVVI   $15, V14
	VMVVI   $-16, V14
	VMVVV   V1, V4
	VMVVX   X10, V4
	VMVXS   V4, X10
	VFMVSF  F10, X11
	RET

TEXT ·shiftsSliding(SB), NOSPLIT, $0
	VSLLVI         $0, V28, V30
	VSLLVI         $31, V28, V30
	VSRLVI         $25, V29, V29
	VSRAVI         $31, V4, V5
	VNSRLWI        $31, V6, V7
	VNSRAWI        $0, V6, V7
	VSLLVV         V1, V2, V3
	VSRLVX         X10, V2, V3
	VSRAVV         V1, V2, V3
	VRORVI         $7, V4, V5
	VRORVI         $31, V4, V5
	VRORVV         V1, V2, V3
	VROLVX         X10, V2, V3
	VSLIDEUPVI     $31, V4, V5
	VSLIDEUPVX     X10, V4, V5
	VSLIDEDOWNVI   $0, V4, V5
	VSLIDEDOWNVX   X10, V4, V5
	VFSLIDE1UPVF   F10, V4, V5
	VFSLIDE1DOWNVF F10, V4, V5
	VRGATHERVI     $31, V2, V3
	VRGATHERVV     V1, V2, V3
	VRGATHERVX     X10, V2, V3
	RET

TEXT ·compareMask(SB), NOSPLIT, $0
	VMSEQVV  V1, V2, V0
	VMSEQVX  X10, V2, V0
	VMSEQVI  $0, V2, V0
	VMSNEVI  $-16, V2, V0
	VMSLTVI  $15, V2, V0
	VMSLTUVI $15, V2, V0
	VMSLEVI  $-1, V2, V0
	VMSGEVI  $15, V2, V0
	VMSGEUVI $0, V2, V0
	VMSGTVV  V1, V2, V0
	VMSLEVV  V1, V2, V0
	VMFEQVF  F10, V2, V0
	VMFLTVF  F10, V2, V0
	VMFGEVF  F10, V2, V0
	VMANDMM  V1, V2, V3
	VMNANDMM V1, V2, V3
	VMANDNMM V1, V2, V3
	VMORMM   V1, V2, V3
	VMXORMM  V1, V2, V3
	VMXNORMM V1, V2, V3
	VMNORMM  V1, V2, V3
	VMORNMM  V1, V2, V3
	VMCLRM   V1
	VMSETM   V1
	VMNOTM   V1, V2
	VCPOPM   V0, X6
	VFIRSTM  V0, X7
	VIOTAM   V0, X5
	VMSBFM   V0, V1
	VMSIFM   V0, V1
	VMSOFM   V0, V1
	RET

TEXT ·carryMerge(SB), NOSPLIT, $0
	VADCVVM    V1, V2, V0, V3
	VADCVXM    X10, V2, V0, V3
	VADCVIM    $15, V2, V0, V3
	VMADCVV    V1, V2, V3
	VMADCVX    X10, V2, V3
	VMADCVI    $-16, V2, V3
	VSBCVVM    V1, V2, V0, V3
	VSBCVXM    X10, V2, V0, V3
	VSBCVVM    V1, V2, V0, V3
	VSBCVXM    X10, V2, V0, V3
	VMADCVV    V1, V2, V3
	VMADCVX    X10, V2, V3
	VMADCVI    $0, V2, V3
	VMADCVVM   V1, V2, V0, V3
	VMERGEVVM  V1, V2, V0, V3
	VMERGEVXM  X10, V2, V0, V3
	VMERGEVIM  $15, V2, V0, V3
	VFMERGEVFM F10, V2, V0, V3
	RET

TEXT ·reduceWiden(SB), NOSPLIT, $0
	VREDSUMVS    V1, V2, V3
	VREDMAXUVS   V1, V2, V3
	VREDMINVS    V1, V2, V3
	VREDANDVS    V1, V2, V3
	VREDORVS     V1, V2, V3
	VREDXORVS    V1, V2, V3
	VWREDSUMUVS  V1, V2, V3
	VWREDSUMVS   V1, V2, V3
	VFWREDOSUMVS V1, V2, V3
	VFWREDUSUMVS V1, V2, V3
	VWADDUVV     V1, V2, V3
	VWADDWV      V1, V2, V3
	VWSUBUVV     V1, V2, V3
	VWSUBWV      V1, V2, V3
	VWADDUWX     X10, V2, V3
	VWADDWX      X10, V2, V3
	VMULVV       V1, V2, V3
	VMULHUVV     V1, V2, V3
	VMULHSUVV    V1, V2, V3
	VDIVUVV      V1, V2, V3
	VREMVV       V1, V2, V3
	VSMULVV      V1, V2, V3
	VCLMULVV     V1, V2, V3
	VCLMULHVX    X10, V2, V3
	RET

TEXT ·fpVec(SB), NOSPLIT, $0
	VFADDVV     V1, V2, V3
	VFADDVF     F10, V2, V3
	VFSUBVF     F10, V2, V3
	VFMULVV     V1, V2, V3
	VFDIVVF     F10, V2, V3
	VFRSUBVF    F10, V2, V3
	VFMINVV     V1, V2, V3
	VFMAXVF     F10, V2, V3
	VFMACCVV    V1, V2, V3
	VFMACCVF    F10, V2, V3
	VFMSACVV    V1, V2, V3
	VFNMSACVF   F10, V2, V3
	VFMADDVV    V1, V2, V3
	VFNMADDVF   F10, V2, V3
	VFWMACCVV   V1, V2, V3
	VFWMSACVF   F10, V2, V3
	VFSQRTV     V4, V5
	VFCLASSV    V4, V5
	VFREC7V     V4, V5
	VFRSQRT7V   V4, V5
	VFCVTXFV    V4, V5
	VFCVTRTZXFV V4, V5
	VFNCVTFFW   V4, V5
	VFWCVTFFV   V4, V5
	VSEXTVF2    V4, V5
	VZEXTVF8    V4, V5
	RET