121 lines
2.3 KiB
ArmAsm
121 lines
2.3 KiB
ArmAsm
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// Seed corpus for FuzzAssembleLOONG64: the branches over their offset range,
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// the jumps, the bit-field pair at the msb/lsb boundaries, the ALSL shift
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// window, RDTIME, the system instructions, the constant materialisation
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// chain and the register-class moves.
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#include "textflag.h"
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TEXT ·branches(SB), NOSPLIT, $0
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BEQ R4, R5, b1
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BNE R4, R5, b2
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BLT R4, R5, b1
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BGE R4, R5, b2
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BLTU R4, R5, b1
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BGEU R4, R5, b2
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BEQZ R6, b1
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BNEZ R7, b2
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BLTZ R8, b1
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BGEZ R9, b2
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BLEZ R10, b1
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BGTZ R11, b2
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BFPT b1
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BFPF b2
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b1:
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MOVV R1, R2
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b2:
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MOVV R2, R1
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BEQ R4, R5, b1
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RET
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TEXT ·jumps(SB), NOSPLIT, $0
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JMP j1
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JAL (R30)
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JIRL R0, R4, 8
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JIRL R1, R5, 0
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CALL runtime·morestack_noctxt(SB)
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j1:
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JMP -3(PC)
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RET
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TEXT ·bitfield(SB), NOSPLIT, $0
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BSTRINSW $3, R4, $0, R5
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BSTRINSV $7, R4, $0, R5
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BSTRINSV $31, R6, $0, R7
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BSTRINSV $63, R6, $32, R7
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BSTRPICKW $3, R4, $0, R5
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BSTRPICKV $6, R7, $0, R8
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BSTRPICKV $63, R6, $32, R7
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ALSLW $1, R4, R5, R6
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ALSLW $4, R7, R8, R9
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ALSLWU $3, R4, R5, R6
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ALSLV $2, R8, R9, R10
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ALSLV $3, R8, R9, R10
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RET
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TEXT ·system(SB), NOSPLIT, $0
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SYSCALL
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DBAR
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DBAR $0
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BREAK $0
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BREAK $32767
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PRELD 0(R4), $0
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PRELD 2047(R4), $31
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RDTIMELW R7, R8
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RDTIMEHW R7, R8
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RDTIMED R20, R21
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RET
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TEXT ·consts(SB), NOSPLIT, $0
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LU12IW R4, $0x12345
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LU12IW R5, $-524288
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LU12IW R6, $1048575
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LU32ID R7, $-524288
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LU52ID $-4096, R8, R9
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LU52ID $4095, R8, R9
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PCALAU12I R10, $0x12345
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PCADDU12I R11, $-524288
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ADDV16 $65536, R11, R12
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ADDV16 $-65536, R11, R12
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MOVV $0x123456789ABCDEF0, R13
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MOVV $-1, R14
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RET
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TEXT ·regClasses(SB), NOSPLIT, $0
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MOVV R4, F5
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MOVV F6, R7
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MOVW R8, F9
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MOVW F10, R11
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MOVV R12, FCC0
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MOVV FCC1, R13
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MOVV R14, FCSR0
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MOVV FCSR3, R15
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FSEL FCC0, F3, F4, F3
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FSEL FCC1, F1, F2
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RET
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TEXT ·memOffsets(SB), NOSPLIT, $0
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MOVB 2047(R4), R5
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MOVB -2048(R4), R5
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MOVH 2047(R4), R5
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MOVW 2047(R4), R5
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MOVV 2047(R4), R5
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MOVW 2048(R4), R5
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MOVW -2048(R4), R5
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MOVW 4095(R4), R5
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MOVW -4096(R4), R5
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MOVW 65536(R4), R5
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MOVW $4(R4), R5
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MOVV $4(R4), R5
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MOVBU -1(R4), R5
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MOVHU 2(R4), R5
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MOVWU -3(R4), R5
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MOVF 8(R4), F5
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MOVD -8(R4), F5
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MOVV (R4)(R5), R6
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RET
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