49 lines
1.3 KiB
ArmAsm
49 lines
1.3 KiB
ArmAsm
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// Carry arithmetic, logical shifts, register aliases with element selectors
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// and the ADC/SBC immediate spellings: the shapes nat_arm64.s, p256 and
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// gcm_arm64.s exercise. Byte-for-byte against go tool asm.
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#include "textflag.h"
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#define acc0 V8
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#define acc1 V9
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#define const0 R15
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#define POLY V15
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// carry pins the ADC/SBC family: the $0 spellings in two and three
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// operands, and the register-carry forms.
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TEXT ·carry(SB), NOSPLIT, $0-0
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ADC $0, R20
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ADC $0, R20, R4
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SBCS $0, R4
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SBCS $0, R4, R12
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SBCS R15, R4, R12
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SBC $0, R1
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ADCSW $0, R2, R3
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RET
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// shift pins the shifted-register forms including ROR, which only the
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// logical family accepts.
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TEXT ·shift(SB), NOSPLIT, $0-0
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ANDW R9@>7, R19, R26
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AND R1@>33, R2, R3
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ADD R1<<11, R2, R3
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SUB R1->33, R2
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ORR R5<<2, R6, R7
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RET
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// vecalias pins the vector aliases with element selectors and the
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// structure loads with aliased members.
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TEXT ·vecalias(SB), NOSPLIT, $0-0
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MOVD $0xC2, R1
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VMOV R1, POLY.D[0]
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VMOV R0, POLY.D[1]
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VEOR POLY.B16, POLY.B16, POLY.B16
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VLD1 (R0), [acc0.B16]
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VLD1.P (R0), [acc0.B16, acc1.B16]
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VST1 [acc0.B16, acc1.B16], (R1)
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VST1.P [acc0.B16, acc1.B16], 32(R1)
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RET
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