49 lines
1.1 KiB
ArmAsm
49 lines
1.1 KiB
ArmAsm
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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// rvcstore exercises the register-relative compressed stores with offsets
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// that set immediate bits 4 and 5, the bare FENCE, and the GOROOT width
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// spellings of the loads and stores, byte-parity-checked against go tool asm.
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#include "textflag.h"
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TEXT ·stores(SB), NOSPLIT, $0
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SD X9, 24(X8)
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SW X10, 16(X11)
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FSD F8, 40(X12)
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LD 24(X8), X9
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LW 16(X11), X10
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FLD 40(X12), F8
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RET
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TEXT ·fence(SB), NOSPLIT, $0
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FENCE
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ECALL
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RET
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// The GOROOT width spellings: MOVW lowers to LW/SW and compresses exactly
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// like the base mnemonic, the byte/half and unsigned forms stay wide.
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TEXT ·argwidths(SB), NOSPLIT, $0-24
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MOVW x+0(FP), X9
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MOVW X9, y+4(FP)
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MOVWU z+8(FP), X10
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MOVB b+12(FP), X11
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MOVBU c+13(FP), X12
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MOVH h+16(FP), X13
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MOVHU u+18(FP), X14
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RET
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TEXT ·spwidths(SB), NOSPLIT, $32-0
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MOVW 4(SP), X9
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MOVW X9, 8(SP)
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MOV 16(SP), X10
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MOV X10, 24(SP)
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RET
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TEXT ·fpwidths(SB), NOSPLIT, $0-16
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MOVD d+0(FP), F8
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MOVD F8, r+8(FP)
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MOVW w+0(FP), X9
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MOVW X9, v+4(FP)
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RET
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