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feat(arch): the same-size shift-immediate family

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Assisted-by: GLM 5.3 Flash
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petrbalvin committed 2026-10-07 21:39:45 +02:00
1 parent eda8b16c5f
commit 1031cd9ae7
4 files changed
+234 -13
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arch/arm64_ext_test.go
+46
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@@ -1779,6 +1779,34 @@ func TestArm64ExtShiftImmGolden(t *testing.T) {
{"ZSQSHL $20, Z8.S, P4.M, Z8.S", "ZSQSHL", ExtFormShiftImmPred,
[]ExtOperand{ExtImmediate(20), ExtVector(8, ExtArrS), ExtPredicate(4, ExtQualMerging), ExtVector(8, ExtArrS)},
0x04469288},
// The same-size right shifts, the accumulator and the extract.
{"ZSRI $6, Z7.D, Z23.D", "ZSRI", ExtFormShiftImmSame,
[]ExtOperand{ExtImmediate(6), ExtVector(7, ExtArrD), ExtVector(23, ExtArrD)},
0x45daf0f7},
{"ZSSRA $6, Z7.D, Z23.D", "ZSSRA", ExtFormShiftImmSame,
[]ExtOperand{ExtImmediate(6), ExtVector(7, ExtArrD), ExtVector(23, ExtArrD)},
0x45dae0f7},
{"ZUSRA $6, Z7.D, Z23.D", "ZUSRA", ExtFormShiftImmSame,
[]ExtOperand{ExtImmediate(6), ExtVector(7, ExtArrD), ExtVector(23, ExtArrD)},
0x45dae4f7},
{"ZSRSRA $6, Z7.D, Z23.D", "ZSRSRA", ExtFormShiftImmSame,
[]ExtOperand{ExtImmediate(6), ExtVector(7, ExtArrD), ExtVector(23, ExtArrD)},
0x45dae8f7},
{"ZURSRA $6, Z7.D, Z23.D", "ZURSRA", ExtFormShiftImmSame,
[]ExtOperand{ExtImmediate(6), ExtVector(7, ExtArrD), ExtVector(23, ExtArrD)},
0x45daecf7},
{"ZASR $6, Z7.D, Z23.D", "ZASR", ExtFormShiftImmSame,
[]ExtOperand{ExtImmediate(6), ExtVector(7, ExtArrD), ExtVector(23, ExtArrD)},
0x04fa90f7},
{"ZASR $6, Z23.B, P1.M, Z23.B", "ZASR", ExtFormShiftImmPredRight,
[]ExtOperand{ExtImmediate(6), ExtVector(23, ExtArrB), ExtPredicate(1, ExtQualMerging), ExtVector(23, ExtArrB)},
0x04008557},
{"ZASRD $6, Z23.B, P1.M, Z23.B", "ZASRD", ExtFormShiftImmPredRight,
[]ExtOperand{ExtImmediate(6), ExtVector(23, ExtArrB), ExtPredicate(1, ExtQualMerging), ExtVector(23, ExtArrB)},
0x04048557},
{"ZXAR $6, Z23.B, Z21.B, Z21.B", "ZXAR", ExtFormShiftImmXar,
[]ExtOperand{ExtImmediate(6), ExtVector(23, ExtArrB), ExtVector(21, ExtArrB), ExtVector(21, ExtArrB)},
0x042a36f5},
} {
in := extInstructionMeta(t, tt.mnem, tt.form, 0, ExtArrNone)
got, err := in.Encode(tt.ops)
@@ -1848,6 +1876,24 @@ func TestArm64ExtShiftImmRejects(t *testing.T) {
{"amount zero", "ZSQSHL", ExtFormShiftImmPred,
[]ExtOperand{ExtImmediate(0), ExtVector(23, ExtArrB), ExtPredicate(1, ExtQualMerging), ExtVector(23, ExtArrB)},
"outside the range 1..7"},
{"same-size arrangements differ", "ZSRI", ExtFormShiftImmSame,
[]ExtOperand{ExtImmediate(6), ExtVector(7, ExtArrB), ExtVector(23, ExtArrH)},
"must match"},
{"same-size amount zero", "ZSRI", ExtFormShiftImmSame,
[]ExtOperand{ExtImmediate(0), ExtVector(7, ExtArrD), ExtVector(23, ExtArrD)},
"outside the range 1..63"},
{"same-size amount at the element size", "ZSRI", ExtFormShiftImmSame,
[]ExtOperand{ExtImmediate(64), ExtVector(7, ExtArrD), ExtVector(23, ExtArrD)},
"outside the range 1..63"},
{"predicated right amount at the element size", "ZASR", ExtFormShiftImmPredRight,
[]ExtOperand{ExtImmediate(8), ExtVector(23, ExtArrB), ExtPredicate(1, ExtQualMerging), ExtVector(23, ExtArrB)},
"outside the range 1..7"},
{"extract read-back mismatch", "ZXAR", ExtFormShiftImmXar,
[]ExtOperand{ExtImmediate(6), ExtVector(23, ExtArrB), ExtVector(21, ExtArrB), ExtVector(20, ExtArrB)},
"the same register Zdn"},
{"extract arrangements differ", "ZXAR", ExtFormShiftImmXar,
[]ExtOperand{ExtImmediate(6), ExtVector(23, ExtArrB), ExtVector(21, ExtArrH), ExtVector(21, ExtArrH)},
"must match"},
} {
in := extInstruction(t, tt.mnem, tt.form)
_, err := in.Encode(tt.ops)