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feat(arch): the same-size shift-immediate family

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Assisted-by: GLM 5.3 Flash
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petrbalvin committed 2026-10-07 21:39:45 +02:00
1 parent eda8b16c5f
commit 1031cd9ae7
4 files changed
+234 -13
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asm/arm64_ext_asm_test.go
+15
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@@ -994,6 +994,16 @@ func TestArm64AssembleExtensionShiftImmGolden(t *testing.T) {
{"ZSQSHRNT $16, Z5.D, Z4.S", 0x457024a4},
{"ZSSHLLB $0, Z3.B, Z2.H", 0x4508a062},
{"ZSQSHL $20, Z8.S, P4.M, Z8.S", 0x04469288},
// The same-size right shifts, the accumulator and the extract.
{"ZSRI $6, Z7.D, Z23.D", 0x45daf0f7},
{"ZSSRA $6, Z7.D, Z23.D", 0x45dae0f7},
{"ZUSRA $6, Z7.D, Z23.D", 0x45dae4f7},
{"ZSRSRA $6, Z7.D, Z23.D", 0x45dae8f7},
{"ZURSRA $6, Z7.D, Z23.D", 0x45daecf7},
{"ZASR $6, Z7.D, Z23.D", 0x04fa90f7},
{"ZASR $6, Z23.B, P1.M, Z23.B", 0x04008557},
{"ZASRD $6, Z23.B, P1.M, Z23.B", 0x04048557},
{"ZXAR $6, Z23.B, Z21.B, Z21.B", 0x042a36f5},
}
for _, tt := range tests {
words := assembleArm64Words(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")
@@ -1029,6 +1039,11 @@ func TestArm64AssembleExtensionShiftImmRefusals(t *testing.T) {
{"ZSQSHL $6, Z23.B, P1.M, Z22.B", "the same register Zdn"},
{"ZSQSHL $6, Z23.Q, P1.M, Z23.Q", "no size encoding"},
{"ZSQSHL $8, Z23.B, P1.M, Z23.B", "outside the range 1..7"},
{"ZSRI $6, Z7.B, Z23.H", "must match"},
{"ZSRI $0, Z7.D, Z23.D", "outside the range 1..63"},
{"ZASR $8, Z23.B, P1.M, Z23.B", "outside the range 1..7"},
{"ZXAR $6, Z23.B, Z21.B, Z20.B", "the same register Zdn"},
{"ZXAR $6, Z23.B, Z21.H, Z21.H", "must match"},
}
for _, tt := range tests {
got := assembleArm64SrcError(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")