feat(asm): encode the arm64 SVE gather loads and scatter stores

Assisted-by: GLM 5.3
2026-10-07 13:51:10 +02:00
1 parent 6faf850793
commit 104bea036b
@@ -1322,3 +1322,87 @@ func TestArm64ExtStage3Golden(t *testing.T) {
 		}
 	}
 }
+
+// extSveRow finds the gather/scatter row whose mnemonic, addressing mode,
+// base size, shift and list arrangement all match.
+func extSveRow(t *testing.T, mnem string, mode uint8, shift int, base, arr ExtArrangement) ExtInstr {
+	t.Helper()
+	for _, in := range Extensions(ARM64) {
+		if in.Name == mnem && in.Form.Arity() == 3 && in.SveMode == mode &&
+			in.SveShift == shift && in.SveBase == base && in.Arr == arr {
+			return in
+		}
+	}
+	t.Fatalf("no extended %s with mode %d, shift %d, base %s and list %s", mnem, mode, shift, base, arr)
+	return ExtInstr{}
+}
+
+// TestArm64ExtGatherGolden pins the gather/scatter family against the
+// toolchain-generated corpus at the metadata layer: one row per addressing
+// mode, the want word that corpus line's own encoding.  The asm-level
+// TestArm64AssembleExtensionGatherGolden pins every corpus line of the
+// scope end to end; these rows prove the forms and the operand builders
+// the registry exposes.
+func TestArm64ExtGatherGolden(t *testing.T) {
+	for _, tt := range []struct {
+		name  string
+		mnem  string
+		mode  uint8
+		shift int
+		base  ExtArrangement
+		arr   ExtArrangement
+		ops   []ExtOperand
+		want  uint32
+	}{
+		{"ZLD1B (R6)(R14), P4.Z, [Z13.B]", "ZLD1B", extMemPair, 0, ExtArrNone, ExtArrB,
+			[]ExtOperand{ExtSveMemPair(6, 0, 14, false), ExtPredicate(4, ExtQualZeroing), ExtVector(13, ExtArrB)},
+			0xa40651cd},
+		{"ZLD1H (R6<<1)(R14), P4.Z, [Z13.H]", "ZLD1H", extMemPair, 1, ExtArrNone, ExtArrH,
+			[]ExtOperand{ExtSveMemPair(6, 1, 14, false), ExtPredicate(4, ExtQualZeroing), ExtVector(13, ExtArrH)},
+			0xa4a651cd},
+		{"ZLD1B (Z10.D)(R19), P3.Z, [Z15.D]", "ZLD1B", extMemVecOff, 0, ExtArrD, ExtArrD,
+			[]ExtOperand{ExtSveMemVector(10, ExtArrD, 0, 19), ExtPredicate(3, ExtQualZeroing), ExtVector(15, ExtArrD)},
+			0xc44ace6f},
+		{"ZLD1D (Z23.D<<3)(R24), P1.Z, [Z22.D]", "ZLD1D", extMemVecOff, 3, ExtArrD, ExtArrD,
+			[]ExtOperand{ExtSveMemVector(23, ExtArrD, 3, 24), ExtPredicate(1, ExtQualZeroing), ExtVector(22, ExtArrD)},
+			0xc5f7c716},
+		{"ZLD1H (Z4.S.UXTW<<1)(R3), P3.Z, [Z4.S]", "ZLD1H", extMemExt32, 1, ExtArrS, ExtArrS,
+			[]ExtOperand{ExtSveMemExtended(4, false, 1, 3), ExtPredicate(3, ExtQualZeroing), ExtVector(4, ExtArrS)},
+			0x84a44c64},
+		{"ZLD1SB (Z4.S.UXTW)(R3), P3.Z, [Z4.S]", "ZLD1SB", extMemExt32, 0, ExtArrS, ExtArrS,
+			[]ExtOperand{ExtSveMemExtended(4, false, 0, 3), ExtPredicate(3, ExtQualZeroing), ExtVector(4, ExtArrS)},
+			0x84040c64},
+		{"ZLD1B 6(Z7.S), P4.Z, [Z13.S]", "ZLD1B", extMemImm, 0, ExtArrS, ExtArrS,
+			[]ExtOperand{ExtSveMemImmediate(7, ExtArrS, 6), ExtPredicate(4, ExtQualZeroing), ExtVector(13, ExtArrS)},
+			0x8426d0ed},
+		{"ZLD1D 8(Z14.D), P6.Z, [Z6.D]", "ZLD1D", extMemImm, 3, ExtArrD, ExtArrD,
+			[]ExtOperand{ExtSveMemImmediate(14, ExtArrD, 8), ExtPredicate(6, ExtQualZeroing), ExtVector(6, ExtArrD)},
+			0xc5a1d9c6},
+		{"ZLDFF1SW 12(Z0.D), P6.Z, [Z25.D]", "ZLDFF1SW", extMemImm, 2, ExtArrD, ExtArrD,
+			[]ExtOperand{ExtSveMemImmediate(0, ExtArrD, 12), ExtPredicate(6, ExtQualZeroing), ExtVector(25, ExtArrD)},
+			0xc523b819},
+		{"ZST1B [Z7.D], P4, (R21)(R7)", "ZST1B", extMemPair, 0, ExtArrNone, ExtArrD,
+			[]ExtOperand{ExtVector(7, ExtArrD), ExtPredicateSized(4, ExtArrNone), ExtSveMemPair(21, 0, 7, false)},
+			0xe47550e7},
+		{"ZST1D [Z8.D], P3, (Z6.D)(RSP)", "ZST1D", extMemVecOff, 0, ExtArrD, ExtArrD,
+			[]ExtOperand{ExtVector(8, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtOperand{Kind: ExtSveMem, Reg: 6, Arr: ExtArrD, Off: 31, Reg31: 2, BaseVec: true}},
+			0xe586afe8},
+		{"ZST1W [Z16.D], P2, (Z5.D)", "ZST1W", extMemVecBase, 0, ExtArrD, ExtArrD,
+			[]ExtOperand{ExtVector(16, ExtArrD), ExtPredicateSized(2, ExtArrNone), ExtSveMemVector(5, ExtArrD, 0, -1)},
+			0xe540a8b0},
+		{"ZST1H [Z8.S], P3, 6(Z15.S)", "ZST1H", extMemImm, 1, ExtArrS, ExtArrS,
+			[]ExtOperand{ExtVector(8, ExtArrS), ExtPredicateSized(3, ExtArrNone), ExtSveMemImmediate(15, ExtArrS, 6)},
+			0xe4e3ade8},
+	} {
+		mode := tt.mode
+		in := extSveRow(t, tt.mnem, mode, tt.shift, tt.base, tt.arr)
+		got, err := in.Encode(tt.ops)
+		if err != nil {
+			t.Errorf("%s: encode: %v", tt.name, err)
+			continue
+		}
+		if want := hex.EncodeToString(extWordLE(tt.want)); hex.EncodeToString(got) != want {
+			t.Errorf("%s:\n  got  %x\n  want %s", tt.name, got, want)
+		}
+	}
+}