feat(arch): add the scaled index to the amd64 memory operands

Assisted-by: GLM 5.3 Flash

arch/arm64_ext.go

@@ -175,6 +175,14 @@ type ExtOperand struct {
 	// every lane of the destination, which the encoder lays down as EVEX.b.
 	// Only the memory positions of the entries that carry Bcast accept it.
 	Broadcast bool
+	// Index and Scale spell the scaled index of an amd64 memory operand,
+	// the SIB byte's shape: base plus index times scale.  Scale carries the
+	// byte multiplier 1, 2, 4 or 8, and HasIndex separates a spelled index
+	// from the plain base-plus-displacement operand.  The index is a
+	// general register 0..15, and RSP is no index.
+	Index    int
+	Scale    int
+	HasIndex bool
 }
 
 // ExtVector builds a scalable vector operand, ADD Z1.S style.
@@ -213,6 +221,14 @@ func ExtBroadcast(base int, disp int64) ExtOperand {
 	return ExtOperand{Kind: ExtMem, Reg: base, Imm: disp, Broadcast: true}
 }
 
+// ExtScaledMemory builds the base-plus-scaled-index memory operand, the amd64
+// SIB shape: the base and the index are 64-bit general register numbers,
+// 0..15, the scale is the byte multiplier 1, 2, 4 or 8, and the displacement
+// keeps the plain ModR/M disp8 or disp32 semantics.
+func ExtScaledMemory(base, index, scale int, disp int64) ExtOperand {
+	return ExtOperand{Kind: ExtMem, Reg: base, Imm: disp, Index: index, Scale: scale, HasIndex: true}
+}
+
 // ExtField is one named field of the 32-bit encoding word: a bit offset from
 // the least significant end and the field's width.
 type ExtField struct {