feat(asm): complete the EVEX conversions, narrowing and mask-vector moves
Assisted-by: Qwen 3.8 Max Preview
This commit is contained in:
+107
-4
@@ -308,6 +308,75 @@ var evexTable = map[string]evexSpec{
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// EVEX.66.0F3A — half-precision convert back ($imm, src, dst: reg=src,
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// rm=dst, imm8 — the extract layout).
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"VCVTPS2PH": {3, 0x1D, 0, 1, -1, vexExtract, [3]int{8, 16, 32}},
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// EVEX — unsigned and truncating conversions. The PD sources are the
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// wide operand (the bare names are 512-bit only, the X/Y spellings fix
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// the length); the PS/UQQ destinations are wide and follow the
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// destination.
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"VCVTPD2PS": {1, 0x5A, 1, 1, -1, vexRMSrcLen, [3]int{0, 0, 64}},
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"VCVTPD2PSX": {1, 0x5A, 1, 1, -1, vexRMSrcLen, [3]int{16, 0, 0}},
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"VCVTPD2PSY": {1, 0x5A, 1, 1, -1, vexRMSrcLen, [3]int{0, 32, 0}},
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"VCVTPD2UDQ": {1, 0x79, 1, 0, -1, vexRMSrcLen, [3]int{0, 0, 64}},
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"VCVTPD2UDQX": {1, 0x79, 1, 0, -1, vexRMSrcLen, [3]int{16, 0, 0}},
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"VCVTPD2UDQY": {1, 0x79, 1, 0, -1, vexRMSrcLen, [3]int{0, 32, 0}},
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"VCVTTPD2UDQ": {1, 0x78, 1, 0, -1, vexRMSrcLen, [3]int{0, 0, 64}},
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"VCVTTPD2UDQX": {1, 0x78, 1, 0, -1, vexRMSrcLen, [3]int{16, 0, 0}},
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"VCVTTPD2UDQY": {1, 0x78, 1, 0, -1, vexRMSrcLen, [3]int{0, 32, 0}},
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"VCVTTPD2UQQ": {1, 0x78, 1, 1, -1, vexRM, [3]int{16, 32, 64}},
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"VCVTPS2UDQ": {1, 0x79, 0, 0, -1, vexRM, [3]int{16, 32, 64}},
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"VCVTTPS2UDQ": {1, 0x78, 0, 0, -1, vexRM, [3]int{16, 32, 64}},
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"VCVTPS2UQQ": {1, 0x79, 0, 1, -1, vexRM, [3]int{8, 16, 32}},
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"VCVTTPS2UQQ": {1, 0x78, 0, 1, -1, vexRM, [3]int{8, 16, 32}},
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"VCVTTPD2QQ": {1, 0x7A, 1, 1, -1, vexRM, [3]int{16, 32, 64}},
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"VCVTTPS2QQ": {1, 0x7A, 0, 1, -1, vexRM, [3]int{8, 16, 32}},
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"VCVTUQQ2PD": {1, 0x7A, 1, 2, -1, vexRM, [3]int{16, 32, 64}},
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"VCVTUQQ2PS": {1, 0x7A, 1, 3, -1, vexRMSrcLen, [3]int{0, 0, 64}},
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"VCVTUQQ2PSX": {1, 0x7A, 1, 3, -1, vexRMSrcLen, [3]int{16, 0, 0}},
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"VCVTUQQ2PSY": {1, 0x7A, 1, 3, -1, vexRMSrcLen, [3]int{0, 32, 0}},
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"VCVTQQ2PSX": {1, 0x5B, 1, 0, -1, vexRMSrcLen, [3]int{16, 0, 0}},
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"VCVTQQ2PSY": {1, 0x5B, 1, 0, -1, vexRMSrcLen, [3]int{0, 32, 0}},
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// EVEX.66.0F38 — the remaining sign/zero-extending moves (narrow
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// source; disp8×N follows its size).
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"VPMOVSXBD": {2, 0x21, 0, 1, -1, vexRM, [3]int{4, 8, 16}},
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"VPMOVSXBQ": {2, 0x22, 0, 1, -1, vexRM, [3]int{2, 4, 8}},
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"VPMOVSXWD": {2, 0x23, 0, 1, -1, vexRM, [3]int{8, 16, 32}},
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"VPMOVSXWQ": {2, 0x24, 0, 1, -1, vexRM, [3]int{4, 8, 16}},
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"VPMOVZXBD": {2, 0x31, 0, 1, -1, vexRM, [3]int{4, 8, 16}},
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"VPMOVZXBQ": {2, 0x32, 0, 1, -1, vexRM, [3]int{2, 4, 8}},
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"VPMOVZXWD": {2, 0x33, 0, 1, -1, vexRM, [3]int{8, 16, 32}},
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"VPMOVZXWQ": {2, 0x34, 0, 1, -1, vexRM, [3]int{4, 8, 16}},
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"VPMOVZXDQ": {2, 0x35, 0, 1, -1, vexRM, [3]int{8, 16, 32}},
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// EVEX.F3.0F38 — the remaining narrowing stores (vector source in reg,
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// narrow destination in r/m): signed, unsigned and the D/Q truncations.
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"VPMOVSDB": {2, 0x21, 0, 2, -1, vexRMRev, [3]int{4, 8, 16}},
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"VPMOVSQB": {2, 0x22, 0, 2, -1, vexRMRev, [3]int{2, 4, 8}},
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"VPMOVSDW": {2, 0x23, 0, 2, -1, vexRMRev, [3]int{8, 16, 32}},
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"VPMOVSQW": {2, 0x24, 0, 2, -1, vexRMRev, [3]int{4, 8, 16}},
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"VPMOVSQD": {2, 0x25, 0, 2, -1, vexRMRev, [3]int{8, 16, 32}},
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"VPMOVSWB": {2, 0x20, 0, 2, -1, vexRMRev, [3]int{8, 16, 32}},
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"VPMOVUSWB": {2, 0x10, 0, 2, -1, vexRMRev, [3]int{8, 16, 32}},
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"VPMOVUSDB": {2, 0x11, 0, 2, -1, vexRMRev, [3]int{4, 8, 16}},
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"VPMOVUSQB": {2, 0x12, 0, 2, -1, vexRMRev, [3]int{2, 4, 8}},
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"VPMOVUSDW": {2, 0x13, 0, 2, -1, vexRMRev, [3]int{8, 16, 32}},
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"VPMOVUSQW": {2, 0x14, 0, 2, -1, vexRMRev, [3]int{4, 8, 16}},
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"VPMOVUSQD": {2, 0x15, 0, 2, -1, vexRMRev, [3]int{8, 16, 32}},
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"VPMOVDB": {2, 0x31, 0, 2, -1, vexRMRev, [3]int{4, 8, 16}},
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"VPMOVQW": {2, 0x34, 0, 2, -1, vexRMRev, [3]int{4, 8, 16}},
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// EVEX.F3.0F38 — mask/vector conversions: M2* moves an opmask register
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// into a vector (rm = K source, reg = vector destination), *2M does the
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// reverse (reg = K destination, rm = vector source, the length follows
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// the vector).
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"VPMOVM2B": {2, 0x28, 0, 2, -1, vexRM, [3]int{16, 32, 64}},
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"VPMOVM2W": {2, 0x28, 1, 2, -1, vexRM, [3]int{16, 32, 64}},
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"VPMOVM2D": {2, 0x38, 0, 2, -1, vexRM, [3]int{16, 32, 64}},
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"VPMOVM2Q": {2, 0x38, 1, 2, -1, vexRM, [3]int{16, 32, 64}},
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"VPMOVB2M": {2, 0x29, 0, 2, -1, vexRM, [3]int{16, 32, 64}},
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"VPMOVW2M": {2, 0x29, 1, 2, -1, vexRM, [3]int{16, 32, 64}},
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"VPMOVD2M": {2, 0x39, 0, 2, -1, vexRM, [3]int{16, 32, 64}},
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"VPMOVQ2M": {2, 0x39, 1, 2, -1, vexRM, [3]int{16, 32, 64}},
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// EVEX.128/256/512.66.0F38.W0 — sign-extend dwords to qwords; the memory
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// operand is the narrow source, so disp8×N follows its size (8/16/32 for
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// the xmm/ymm/zmm destination lengths).
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@@ -543,6 +612,9 @@ var evexRound = map[string]bool{
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"VSCALEFPD": true, "VSCALEFPS": true, "VSCALEFSD": true, "VSCALEFSS": true,
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"VGETEXPPD": true, "VGETEXPPS": true, "VGETEXPSD": true, "VGETEXPSS": true,
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"VCVTDQ2PS": true, "VCVTPS2QQ": true, "VCVTQQ2PS": true, "VCVTPD2UQQ": true,
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"VCVTPD2PS": true, "VCVTPD2UDQ": true, "VCVTTPD2UDQ": true, "VCVTTPD2UQQ": true,
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"VCVTPS2UDQ": true, "VCVTTPS2UDQ": true, "VCVTPS2UQQ": true, "VCVTTPS2UQQ": true,
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"VCVTTPD2QQ": true, "VCVTTPS2QQ": true, "VCVTUQQ2PD": true, "VCVTUQQ2PS": true,
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}
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// evexBcstN maps an instruction accepting .BCST to the broadcast element
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@@ -562,6 +634,9 @@ var evexBcstN = map[string]int{
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"VRANGEPD": 8, "VRANGEPS": 4,
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"VCVTDQ2PS": 4, "VCVTPS2QQ": 4, "VCVTQQ2PS": 8,
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"VCVTUDQ2PD": 4, "VCVTUDQ2PS": 4,
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"VCVTPD2PS": 8, "VCVTPD2UDQ": 8, "VCVTTPD2UDQ": 8, "VCVTTPD2UQQ": 8,
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"VCVTPS2UDQ": 4, "VCVTTPS2UDQ": 4, "VCVTPS2UQQ": 4, "VCVTTPS2UQQ": 4,
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"VCVTTPD2QQ": 8, "VCVTTPS2QQ": 4, "VCVTUQQ2PD": 8, "VCVTUQQ2PS": 8,
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}
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// splitMask extracts an explicit mask register (K1–K7) from the operand list,
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@@ -591,6 +666,18 @@ func splitMask(ops []Operand) ([]Operand, int, error) {
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// operands; the mnemonic suffix carries zeroing, rounding/SAE and
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// broadcast.
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func (e *enc) encodeEvex(mnemUpper string, ops []Operand, sfx evexSuffix) error {
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// The mask/vector conversions take the K register as a genuine operand
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// (source or destination), not as a mask, and accept no suffixes.
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if evexKOperand[mnemUpper] {
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if sfx.any() {
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return fmt.Errorf("%s takes no EVEX suffixes", mnemUpper)
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}
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spec, ok := evexTable[mnemUpper]
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if !ok {
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return fmt.Errorf("unsupported instruction %q", mnemUpper)
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}
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return e.encodeEvexRM(spec, ops, 0, sfx)
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}
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spec, inTable := evexTable[mnemUpper]
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if inTable {
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if (sfx.rounding >= 0 || sfx.sae) && !evexRound[mnemUpper] {
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@@ -713,17 +800,25 @@ func (e *enc) encodeEvexNDS3(spec evexSpec, ops []Operand, mask int, sfx evexSuf
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}
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// encodeEvexRM encodes the two-operand form: OP src, dst (reg=dst, rm=src,
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// no vvvv), e.g. VCVTQQ2PD.
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// no vvvv), e.g. VCVTQQ2PD. The destination may be an opmask register (the
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// *2M mask conversions), in which case the vector length comes from the
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// source.
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func (e *enc) encodeEvexRM(spec evexSpec, ops []Operand, mask int, sfx evexSuffix) error {
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if len(ops) != 2 {
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return fmt.Errorf("EVEX two-operand instruction expects 2 operands, got %d", len(ops))
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}
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src, dst := ops[0], ops[1]
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dstReg, ok := dst.(Reg)
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if !ok || !dstReg.isVec() {
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return fmt.Errorf("EVEX destination must be a vector register")
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if !ok || (!dstReg.isVec() && !dstReg.mask) {
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return fmt.Errorf("EVEX destination must be a vector or mask register")
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}
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return e.emitEvexFields(spec, dstReg.vecLenBit(), dstReg.idx, -1, src, mask, sfx)
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ll := dstReg.vecLenBit()
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if dstReg.mask {
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if r, ok := src.(Reg); ok && r.isVec() {
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ll = r.vecLenBit()
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}
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}
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return e.emitEvexFields(spec, ll, dstReg.idx, -1, src, mask, sfx)
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}
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// encodeEvexImmRM encodes the immediate shuffle form: OP $imm, src, dst
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@@ -1260,6 +1355,14 @@ func (e *enc) encodeScatter(upper string, ss gatherSpec, ops []Operand, sfx evex
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return e.emitEvexFields(evex, ll, src.idx, -1, vsib, mask, sfx)
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}
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// evexKOperand lists the instructions whose K register is a genuine operand
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// (the source or destination of a mask/vector conversion) rather than a
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// mask modifier — the M2 and 2M conversions. They take no masking.
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var evexKOperand = map[string]bool{
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"VPMOVM2B": true, "VPMOVM2W": true, "VPMOVM2D": true, "VPMOVM2Q": true,
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"VPMOVB2M": true, "VPMOVW2M": true, "VPMOVD2M": true, "VPMOVQ2M": true,
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}
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// kmovSpec describes a KMOV width: the opcode depends on the operand
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// direction — kk (k/mem → K is 90, k → k uses the same), kmem (K → mem),
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// gprk (GPR/mem → K), kgpr (K → GPR) — and the GPR forms carry a mandatory
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