style: replace em and en dashes across sources
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+14
-14
@@ -21,7 +21,7 @@ var aluOp = map[string]struct {
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}
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// unaryOp maps INC/DEC/NEG/NOT to their /digit and base opcode. INC/DEC use
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// the 0xFE/0xFF group (the short 0x40–0x4F forms are REX prefixes in 64-bit
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// the 0xFE/0xFF group (the short 0x40-0x4F forms are REX prefixes in 64-bit
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// mode); NEG/NOT use the 0xF6/0xF7 group.
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var unaryOp = map[string]struct {
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digit int
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@@ -33,7 +33,7 @@ var unaryOp = map[string]struct {
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"NEG": {3, 0xF7},
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}
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// shiftOp maps SHL/SHR/SAR to their /digit in the 0xC0/0xC1/0xD0–0xD3 group.
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// shiftOp maps SHL/SHR/SAR to their /digit in the 0xC0/0xC1/0xD0-0xD3 group.
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var shiftOp = map[string]int{
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"SHL": 4,
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"SHR": 5,
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@@ -50,7 +50,7 @@ func (e *enc) encodeMov(ops []Operand, size int) error {
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// Integer scalar XMM moves: MOVQ with an XMM operand is the SSE2
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// packed-quadword move, NOT a GPR move: mem→xmm encodes as F3 0F 7E
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// (reg = dst, no REX.W — the Go assembler's form), xmm→mem as
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// (reg = dst, no REX.W, the Go assembler's form), xmm→mem as
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// 66 0F D6 (rm = xmm). Register forms against a GPR use the MOVD
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// opcodes with REX.W instead: 66 REX.W 0F 6E (gpr→xmm) and
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// 66 REX.W 0F 7E (xmm→gpr); the memory opcodes with a register r/m
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@@ -103,7 +103,7 @@ func (e *enc) encodeMov(ops []Operand, size int) error {
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switch src := src.(type) {
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case Reg:
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if dstIsReg {
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// MOV r/m, r: 0x88/0x89, reg=src, rm=dst — the form the Go
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// MOV r/m, r: 0x88/0x89, reg=src, rm=dst, the form the Go
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// assembler emits for register-to-register moves.
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i := newInstr(size, []byte{movRM(size)})
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if err := setRM(i, src, dst, size); err != nil {
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@@ -147,7 +147,7 @@ func (e *enc) encodeMov(ops []Operand, size int) error {
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// a signed int32, choosing per sign:
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// v >= 0: B8+rd imm32 without REX.W (zero-extended by the
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// hardware, REX.B still emitted for R8-R15);
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// v < 0: REX.W C7 /0 imm32 (sign-extended — the plain B8+rd
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// v < 0: REX.W C7 /0 imm32 (sign-extended, the plain B8+rd
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// form would zero-extend and corrupt the value).
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// Out-of-range immediates keep the B8+rd imm64 form.
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if size == 8 && v >= 0 && v <= (1<<31)-1 {
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@@ -226,8 +226,8 @@ func (e *enc) encodeALU(op struct {
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return e.encodeALUImm(op.digit, dst, int64(imm), size)
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}
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// CMP accepts the immediate in the second position too — CMPL CX, $31 is
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// the form the Go assembler itself accepts — and encodes it identically
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// CMP accepts the immediate in the second position too, CMPL CX, $31 is
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// the form the Go assembler itself accepts, and encodes it identically
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// (CMP r/m, imm sets the flags as first − second). No other ALU op takes
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// an immediate destination.
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if imm, ok := dst.(Imm); ok {
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@@ -313,7 +313,7 @@ func (e *enc) encodeALUImm(digit int, dst Operand, imm int64, size int) error {
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i.imm = []byte{byte(int8(imm))}
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return e.emit(i)
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}
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// 0x81 /digit, imm16/imm32 — or the Go assembler's accumulator short
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// 0x81 /digit, imm16/imm32, or the Go assembler's accumulator short
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// form (opcode+5, no ModR/M) when the destination is AX/AL, which it
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// prefers over the generic form exactly here.
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if r, ok := dst.(Reg); ok && r.idx == 0 {
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@@ -339,7 +339,7 @@ func (e *enc) encodeTest(ops []Operand, size int) error {
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}
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src, dst := ops[0], ops[1]
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if imm, ok := src.(Imm); ok {
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// TEST r/m, imm: 0xF6 (8-bit) / 0xF7 /0 — but the Go assembler
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// TEST r/m, imm: 0xF6 (8-bit) / 0xF7 /0, but the Go assembler
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// always uses the accumulator forms (A8/A9, no ModR/M) when the
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// register operand is AL/AX, whatever the immediate's width.
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if r, ok := dst.(Reg); ok && r.idx == 0 {
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@@ -678,7 +678,7 @@ func (e *enc) encodeCmov(upper string, ops []Operand) error {
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}
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// encodeSet encodes a conditional byte set: SET + condition (SETNE, SETEQ, …),
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// always a byte write — 0F 90+cc /0 into a register or memory operand.
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// always a byte write, 0F 90+cc /0 into a register or memory operand.
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func (e *enc) encodeSet(upper string, ops []Operand) error {
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if len(ops) != 1 {
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return fmt.Errorf("SETcc expects 1 operand, got %d", len(ops))
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@@ -711,8 +711,8 @@ var countOp = map[string]struct {
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"POPCNT": {0xB8, 0xF3},
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}
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// encodeCount encodes the bit-scan and bit-count family — BSF (0F BC),
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// BSR (0F BD), TZCNT (F3 0F BC), LZCNT (F3 0F BD) and POPCNT (F3 0F B8) —
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// encodeCount encodes the bit-scan and bit-count family, BSF (0F BC),
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// BSR (0F BD), TZCNT (F3 0F BC), LZCNT (F3 0F BD) and POPCNT (F3 0F B8)
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// with reg = dst and rm = src. The size suffix selects the operand width
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// (BSFQ, TZCNTL, …). Note BSF/BSR leave the destination undefined when the
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// source is zero (unlike their F3-prefixed counterparts); callers must
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@@ -801,8 +801,8 @@ type sseMove struct {
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}
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var sseMoveTable = map[string]sseMove{
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"MOVOU": {0xF3, 0x6F, 0x7F}, // MOVDQU — unaligned octa
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"MOVO": {0x66, 0x6F, 0x7F}, // MOVDQA — aligned octa
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"MOVOU": {0xF3, 0x6F, 0x7F}, // MOVDQU, unaligned octa
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"MOVO": {0x66, 0x6F, 0x7F}, // MOVDQA, aligned octa
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"MOVUPS": {0x00, 0x10, 0x11}, // unaligned packed single
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"MOVAPS": {0x00, 0x28, 0x29}, // aligned packed single
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"MOVUPD": {0x66, 0x10, 0x11}, // unaligned packed double
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