feat(arch): add the packed FP16 arithmetic to the amd64 extension layer

Assisted-by: GLM 5.3 Flash

arch/amd64_ext_test.go

@@ -168,6 +168,30 @@ var amd64GoldenRows = []amd64GoldenRow{
 		[]ExtOperand{ExtXmm(30), ExtGpr32(12)},
 		"62157d087ee6", ""},
 
+	// AVX512-FP16 packed arithmetic, EVEX.NDS.512.MAP5.W0 with no
+	// mandatory prefix.  The GNU vector again sits on high registers.
+	{"vaddph", "VADDPH",
+		[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
+		"6205144058f4", "62 05 14 40 58 f4 vaddph %zmm28,%zmm29,%zmm30"},
+	{"vsubph", "VSUBPH",
+		[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
+		"620514405cf4", "62 05 14 40 5c f4 vsubph %zmm28,%zmm29,%zmm30"},
+	{"vmulph", "VMULPH",
+		[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
+		"6205144059f4", "62 05 14 40 59 f4 vmulph %zmm28,%zmm29,%zmm30"},
+	{"vdivph", "VDIVPH",
+		[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
+		"620514405ef4", "62 05 14 40 5e f4 vdivph %zmm28,%zmm29,%zmm30"},
+	{"vminph", "VMINPH",
+		[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
+		"620514405df4", "62 05 14 40 5d f4 vminph %zmm28,%zmm29,%zmm30"},
+	{"vmaxph", "VMAXPH",
+		[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
+		"620514405ff4", "62 05 14 40 5f f4 vmaxph %zmm28,%zmm29,%zmm30"},
+	{"vsqrtph", "VSQRTPH",
+		[]ExtOperand{ExtZmm(29), ExtZmm(30)},
+		"62057c4851f5", "62 05 7c 48 51 f5 vsqrtph %zmm29,%zmm30"},
+
 	// High registers in a 512-bit form exercise the EVEX extension bits:
 	// with both sources above 15 the B bar and X bar bits clear, while the
 	// destination zmm23 keeps R bar set in byte one (derived from the
@@ -392,7 +416,7 @@ func TestAmd64ExtArchBinding(t *testing.T) {
 			t.Errorf("Extensions(%s) carries %d instructions, want none", a, len(got))
 		}
 	}
-	if got := Extensions(AMD64); len(got) != 39 {
-		t.Errorf("the amd64 layer registers %d instructions, want 39", len(got))
+	if got := Extensions(AMD64); len(got) != 46 {
+		t.Errorf("the amd64 layer registers %d instructions, want 46", len(got))
 	}
 }