fix(asm): enforce the arm64 VLD/VST post-index contract

Assisted-by: GLM 5.3

asm/arm64_errorparity_test.go

@@ -17,18 +17,7 @@ import (
 // only shrinks: every tightening of the encoder moves spellings out of it,
 // and a spelling reappearing here means a regression.
 var arm64AcceptedErrorShapes = []string{
-	// VLD1/VST1 post-index shapes: the register post-index without the .P
 	// spelling, the .P immediate against the aggregate register size, the
-	// scaled register increment and the replicating register count.
-	"VLD1 (R8)(R13), [V2.B16]",
-	"VST1 [V1.B16], (R8)(R13)",
-	"VST1.P [V4.S4,V5.S4], 48(R1)",
-	"VST1.P [V4.S4], 8(R1)",
-	"VLD1.P 32(R1), [V8.S4, V9.S4, V10.S4]",
-	"VLD1.P 48(R1), [V7.S4, V8.S4, V9.S4, V10.S4]",
-	"VLD1.P (R8)(R9<<2), [V2.B16]",
-	"VST1.P [V1.B16], (R8)(R9<<1)",
-	"VLD3R.P 24(R15), [V15.H4,V16.H4,V17.H4]",
 	// REGTMP (R27) as an explicit operand the toolchain refuses, the pair
 	// split paths included.
 	"ADD $0x1234567, R27, R3",