feat(riscv): add MOV pseudo-instruction and RVC compressed encoding
Assisted-by: DeepSeek V4 Pro
This commit is contained in:
+379
-13
@@ -10,39 +10,115 @@ import (
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)
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// assembleRISCV assembles a RISC-V TEXT function body into machine code.
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// It handles the core RV64I/RV64M instruction set with fixed 32-bit encoding.
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// It handles the core RV64IMAFDC instruction set.
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func assembleRISCV(t *ast.Text) ([]byte, map[string]int, error) {
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fi := riscvComputeFrame(t)
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prologue := riscvPrologue(fi)
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// First pass: compute label offsets (all RISC-V instructions are 4 bytes).
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// Labels are offset by the prologue length.
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// Pass 1: collect instructions and compute label offsets assuming 4 bytes
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// per instruction (or 8 for MOV $large-imm). No encoding yet.
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type instrRec struct {
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instr *ast.Instr
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compressed bool
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code []byte
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}
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var recs []instrRec
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offsets := map[string]int{}
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var instrs []*ast.Instr
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pos := len(prologue)
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for _, stmt := range t.Body {
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switch s := stmt.(type) {
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case *ast.Label:
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offsets[s.Name.Text] = pos
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case *ast.Instr:
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instrs = append(instrs, s)
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pos += 4 // all RISC-V instructions are 4 bytes
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recs = append(recs, instrRec{instr: s})
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pos += riscvInstrSize(s)
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}
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}
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// Second pass: encode instructions.
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out := append([]byte(nil), prologue...)
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for _, instr := range instrs {
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code, err := encodeRISCVInstr(instr, pos, offsets, fi)
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// Pass 2: encode each instruction using Pass-1 offsets.
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pc := len(prologue)
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for i := range recs {
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code, err := encodeRISCVInstr(recs[i].instr, pc, offsets, fi)
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if err != nil {
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return nil, nil, fmt.Errorf("%s: %w", instr.Mnemonic.Text, err)
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return nil, nil, fmt.Errorf("%s: %w", recs[i].instr.Mnemonic.Text, err)
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}
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recs[i].code = code
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pc += len(code)
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}
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// Pass 3: try RVC compression.
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for i := range recs {
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if c16, ok := tryCompressRVC(recs[i].instr, fi); ok {
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recs[i].compressed = true
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recs[i].code = []byte{byte(c16), byte(c16 >> 8)}
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}
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}
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// Pass 4: recompute offsets with actual sizes.
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offsets = map[string]int{}
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pos = len(prologue)
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for _, stmt := range t.Body {
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switch s := stmt.(type) {
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case *ast.Label:
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offsets[s.Name.Text] = pos
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case *ast.Instr:
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for _, r := range recs {
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if r.instr == s {
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pos += len(r.code)
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break
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}
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}
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}
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}
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// Pass 5: re-encode branches with corrected offsets, emit uncompressed
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// for instructions that can't be compressed.
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out := append([]byte(nil), prologue...)
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pc = len(prologue)
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for _, r := range recs {
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if r.compressed && !isBranchLike(r.instr.Mnemonic.Text) {
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out = append(out, r.code...)
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pc += len(r.code)
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} else {
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// Re-encode with correct offsets (branches need this).
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code, err := encodeRISCVInstr(r.instr, pc, offsets, fi)
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if err != nil {
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return nil, nil, err
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}
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// Try compression again for this instruction.
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if c16, ok := tryCompressRVC(r.instr, fi); ok {
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code = []byte{byte(c16), byte(c16 >> 8)}
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}
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out = append(out, code...)
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pc += len(code)
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}
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out = append(out, code...)
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pos -= 4 // track remaining
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}
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return out, offsets, nil
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}
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// riscvInstrSize returns the encoded size in bytes of a RISC-V instruction.
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// Most instructions are 4 bytes; MOV with a large immediate is 8 (LUI+ADDIW).
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func riscvInstrSize(instr *ast.Instr) int {
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mnem := instr.Mnemonic.Text
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if mnem == "MOV" && len(instr.Operands) == 2 && isImmOperand(instr.Operands[0]) {
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imm := immFromOperand(instr.Operands[0])
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if imm < -2048 || imm > 2047 {
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return 8 // LUI + ADDIW
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}
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}
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return 4
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}
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// isBranchLike reports whether a mnemonic is a branch or jump that needs
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// recalculated offsets after compression.
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func isBranchLike(mnem string) bool {
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switch mnem {
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case "BEQ", "BNE", "BLT", "BGE", "BLTU", "BGEU", "JMP", "JAL":
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return true
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}
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return false
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}
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// encodeRISCVInstr encodes a single RISC-V instruction.
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func encodeRISCVInstr(instr *ast.Instr, pc int, offsets map[string]int, fi riscvFrameInfo) ([]byte, error) {
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mnem := instr.Mnemonic.Text
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@@ -88,6 +164,11 @@ func encodeRISCVInstr(instr *ast.Instr, pc int, offsets map[string]int, fi riscv
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offset := int32(targetOff - pc)
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word = riscvJType(rd, offset)
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
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// MOV is a pseudo-instruction that the Go assembler uses for loads,
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// stores, register moves and immediate loads.
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case "MOV":
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return encodeRISCVMov(instr, offsets, fi)
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}
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// FP conversion / move instructions use a separate table (rs2 encodes
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@@ -166,6 +247,16 @@ func encodeRISCVInstr(instr *ast.Instr, pc int, offsets map[string]int, fi riscv
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}
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word = riscvRType(enc, rd, rs1, rs2)
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// I-type shift (SLLI, SRLI, SRAI): INSTR rs, $shamt, rd.
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case len(ops) == 3 && isShiftImmInstr(mnem):
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rs1 := regFromOperand(ops[0])
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shamt := int(immFromOperand(ops[1]))
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rd := regFromOperand(ops[2])
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if rd < 0 || rs1 < 0 {
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return nil, fmt.Errorf("invalid register in %s", mnem)
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}
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word = riscvRType(enc, rd, rs1, shamt)
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// AMO atomics: Plan 9 order is INSTR src, (addr), dst.
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case len(ops) == 3 && isAMOInstr(mnem):
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rs2 := regFromOperand(ops[0]) // source value
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@@ -304,6 +395,273 @@ func encodeRISCVInstr(instr *ast.Instr, pc int, offsets map[string]int, fi riscv
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
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}
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// isMemOperand reports whether an operand is a memory reference
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// (frame-relative such as name+off(FP) or register-relative such as (X10)).
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func isMemOperand(op *ast.Operand) bool {
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if op.Addr.Sym != nil && op.Addr.Sym.Pseudo != "" {
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return true // name+off(FP), name+off(SP)
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}
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if op.Addr.Base != "" && op.Addr.Sym == nil {
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return true // (reg)
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}
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return false
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}
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// isImmOperand reports whether an operand is an immediate ($value).
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func isImmOperand(op *ast.Operand) bool {
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if op.Kind == ast.OpImmediate {
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return true
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}
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if op.Imm.HasVal {
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return true
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}
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return false
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}
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// encodeRISCVMov encodes the MOV pseudo-instruction.
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//
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// The Go RISC-V assembler uses MOV for:
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// - MOV name+off(FP), Rd load from frame
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// - MOV Rd, name+off(FP) store to frame
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// - MOV (Rs), Rd register-relative load
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// - MOV Rs, (Rd) register-relative store
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// - MOV Rs, Rd register-to-register move (ADDI $0)
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// - MOV $imm, Rd load immediate (ADDI or LUI+ADDIW)
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func encodeRISCVMov(instr *ast.Instr, offsets map[string]int, fi riscvFrameInfo) ([]byte, error) {
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ops := instr.Operands
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if len(ops) != 2 {
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return nil, fmt.Errorf("MOV expects 2 operands, got %d", len(ops))
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}
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src := ops[0]
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dst := ops[1]
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// Immediate → register.
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if isImmOperand(src) {
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rd := regFromOperand(dst)
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if rd < 0 {
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return nil, fmt.Errorf("MOV $imm: invalid destination register")
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}
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imm := immFromOperand(src)
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return encodeRISCVLoadImm(rd, imm), nil
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}
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// Memory → register (load).
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if isMemOperand(src) && !isMemOperand(dst) {
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rd := regFromOperand(dst)
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rs1, off := memFromOperandWithFrame(src, fi)
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if rd < 0 || rs1 < 0 {
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return nil, fmt.Errorf("MOV load: invalid operand")
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}
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word := riscvIType(riscvEnc{0x03, 0x3, 0x00}, rd, rs1, off)
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
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}
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// Register → memory (store).
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if !isMemOperand(src) && isMemOperand(dst) {
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rs2 := regFromOperand(src)
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rs1, off := memFromOperandWithFrame(dst, fi)
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if rs2 < 0 || rs1 < 0 {
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return nil, fmt.Errorf("MOV store: invalid operand")
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}
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word := riscvSType(riscvEnc{0x23, 0x3, 0x00}, rs1, rs2, off)
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
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}
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// Register → register (ADDI $0, src, dst).
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{
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rs1 := regFromOperand(src)
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rd := regFromOperand(dst)
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if rd < 0 || rs1 < 0 {
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return nil, fmt.Errorf("MOV: invalid register operand")
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}
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word := riscvIType(riscvEnc{0x13, 0x0, 0x00}, rd, rs1, 0)
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
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}
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}
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// encodeRISCVLoadImm encodes loading an immediate into a register.
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// For 12-bit immediates: ADDI $imm, ZERO, rd.
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// For larger: LUI $hi, rd + ADDIW $lo, rd, rd.
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func encodeRISCVLoadImm(rd int, imm int32) []byte {
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if imm >= -2048 && imm <= 2047 {
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word := riscvIType(riscvEnc{0x13, 0x0, 0x00}, rd, 0, imm)
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return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}
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}
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// LUI + ADDIW for larger constants.
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var out []byte
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hi := int32((uint32(imm)+0x800)>>12) << 12 // LUI loads upper 20 bits
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lo := imm - hi
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wordLUI := riscvUType(riscvEnc{0x37, 0x0, 0x00}, rd, hi)
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out = append(out, byte(wordLUI), byte(wordLUI>>8), byte(wordLUI>>16), byte(wordLUI>>24))
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if lo != 0 {
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wordADDIW := riscvIType(riscvEnc{0x1B, 0x0, 0x00}, rd, rd, lo)
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out = append(out, byte(wordADDIW), byte(wordADDIW>>8), byte(wordADDIW>>16), byte(wordADDIW>>24))
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}
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return out
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}
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// tryCompressRVC attempts to compress a RISC-V instruction to its 16-bit
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// RVC form. It returns the compressed instruction word and true on success.
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func tryCompressRVC(instr *ast.Instr, fi riscvFrameInfo) (uint16, bool) {
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mnem := instr.Mnemonic.Text
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ops := instr.Operands
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switch mnem {
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case "RET":
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// RET = JALR X0, 0(X1) → C.JR RA (CR-type: funct4=0x8, rd=0, rs2=1)
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return rvcCR(0x8, 0, 1), true
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case "LD", "MOV":
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// LD rd, offset(SP) → C.LDSP when rd≠0 and uimm[8:3] fits.
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// MOV name+off(FP), rd → load, same compression.
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if mnem == "MOV" && len(ops) == 2 && isImmOperand(ops[0]) {
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return 0, false
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}
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// MOV reg, reg → C.MV (CR-type: funct4=0x8).
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if mnem == "MOV" && len(ops) == 2 && !isMemOperand(ops[0]) && !isMemOperand(ops[1]) && !isImmOperand(ops[0]) {
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rs1 := regFromOperand(ops[0])
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rd := regFromOperand(ops[1])
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if rs1 != -1 && rd != -1 && rs1 != 0 && rd != 0 {
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return rvcCR(0x8, uint32(rd), uint32(rs1)), true
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}
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}
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rd, rs1, imm := extractLDParams(instr, fi)
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if rs1 == 2 && rd != 0 && rd != -1 && imm >= 0 && imm < 512 && imm%8 == 0 {
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return rvcCI(0x3, uint32(rd), uint32(imm)>>3), true
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}
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// MOV reg, mem → store, try C.SDSP.
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if mnem == "MOV" && len(ops) == 2 && !isMemOperand(ops[0]) && isMemOperand(ops[1]) {
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rs2, rs1, imm := extractSDParams(instr, fi)
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if rs1 == 2 && rs2 != -1 && imm >= 0 && imm < 512 && imm%8 == 0 {
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return rvcCSS(0x7, uint32(rs2), uint32(imm)>>3), true
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}
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}
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case "SD":
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// SD rs2, offset(SP) → C.SDSP when uimm[8:3] fits (CSS-type).
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rs2, rs1, imm := extractSDParams(instr, fi)
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if rs1 == 2 && rs2 != -1 && imm >= 0 && imm < 512 && imm%8 == 0 {
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uimm := uint32(imm) >> 3
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return rvcCSS(0x7, uint32(rs2), uimm), true
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}
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case "ADDI":
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rd, rs1, imm := extractITypeParams(instr, fi)
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if rd == -1 || rs1 == -1 {
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return 0, false
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}
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if rd == rs1 && rd != 0 && imm != 0 && imm >= -32 && imm <= 31 {
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// C.ADDI: funct3=0x0, rs1/rd, nzimm[5:0]
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return rvcCI(0x0, uint32(rd), uint32(imm)&0x3F), true
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}
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if rs1 == 0 && rd != 0 && imm >= -32 && imm <= 31 {
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// C.LI: funct3=0x2, rd, imm[5:0]
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return rvcCI(0x2, uint32(rd), uint32(imm)&0x3F), true
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}
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if rs1 != 0 && rd != 0 && imm == 0 {
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// C.MV: funct4=0x8, rd, rs1 (CR-type)
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return rvcCR(0x8, uint32(rd), uint32(rs1)), true
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}
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case "JAL":
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// JAL X0, target → C.J when offset fits in ±2KB.
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if len(ops) >= 1 {
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// For JAL with implicit rd=0 (JMP alias), check target.
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// C.J: funct3=0x5
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// Offset is computed at encode time — we can't check it here.
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return 0, false
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}
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case "JMP":
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// C.J — but offset is computed at encode time.
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return 0, false
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case "BEQ":
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// BEQ rs, ZERO, target → C.BEQZ when offset fits in ±256.
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if len(ops) == 3 {
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rs1 := regFromOperand(ops[0])
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rs2 := regFromOperand(ops[1])
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if rs1 != -1 && rs2 == 0 && isRVCIntReg(rs1) {
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// Could be C.BEQZ but offset computed at encode time.
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return 0, false
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}
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}
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case "BNE":
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// BNE rs, ZERO, target → C.BNEZ when offset fits in ±256.
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if len(ops) == 3 {
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rs1 := regFromOperand(ops[0])
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rs2 := regFromOperand(ops[1])
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if rs1 != -1 && rs2 == 0 && isRVCIntReg(rs1) {
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return 0, false
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}
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}
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case "LUI":
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// LUI rd, imm → C.LUI when rd≠0, rd≠SP, imm nonzero and fits in 6 bits.
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if len(ops) == 2 {
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rd := regFromOperand(ops[0])
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imm := immFromOperand(ops[1])
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if rd != -1 && rd != 0 && rd != 2 && imm != 0 && imm >= 1 && imm <= 63 {
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return rvcCI(0x3, uint32(rd), uint32(imm)&0x3F), true
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}
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}
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case "ADDIW":
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rd, rs1, imm := extractITypeParams(instr, fi)
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if rd == rs1 && rd != 0 && imm >= -32 && imm <= 31 {
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return rvcCI(0x1, uint32(rd), uint32(imm)&0x3F), true
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}
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}
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return 0, false
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}
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// extractLDParams extracts rd, rs1, and immediate offset for a load instruction.
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func extractLDParams(instr *ast.Instr, fi riscvFrameInfo) (rd, rs1 int, imm int32) {
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ops := instr.Operands
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if len(ops) != 2 {
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return -1, -1, 0
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}
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if instr.Mnemonic.Text == "MOV" {
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if isMemOperand(ops[0]) {
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rs1, imm = memFromOperandWithFrame(ops[0], fi)
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rd = regFromOperand(ops[1])
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} else {
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return -1, -1, 0
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}
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} else {
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rs1, imm = memFromOperandWithFrame(ops[0], fi)
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rd = regFromOperand(ops[1])
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}
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return
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}
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// extractSDParams extracts rs2, rs1, and immediate offset for a store instruction.
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func extractSDParams(instr *ast.Instr, fi riscvFrameInfo) (rs2, rs1 int, imm int32) {
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ops := instr.Operands
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if len(ops) != 2 {
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return -1, -1, 0
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}
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rs2 = regFromOperand(ops[0])
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rs1, imm = memFromOperandWithFrame(ops[1], fi)
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return
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}
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// extractITypeParams extracts rd, rs1, and immediate for an I-type instruction.
|
||||
func extractITypeParams(instr *ast.Instr, fi riscvFrameInfo) (rd, rs1 int, imm int32) {
|
||||
ops := instr.Operands
|
||||
if len(ops) != 3 {
|
||||
return -1, -1, 0
|
||||
}
|
||||
rs1 = regFromOperand(ops[0])
|
||||
imm = immFromOperand(ops[1])
|
||||
rd = regFromOperand(ops[2])
|
||||
return
|
||||
}
|
||||
|
||||
// Instruction type classifiers.
|
||||
func isRTypeInstr(m string) bool {
|
||||
switch m {
|
||||
@@ -316,6 +674,14 @@ func isRTypeInstr(m string) bool {
|
||||
return false
|
||||
}
|
||||
|
||||
func isShiftImmInstr(m string) bool {
|
||||
switch m {
|
||||
case "SLLI", "SRLI", "SRAI", "SLLIW", "SRLIW", "SRAIW":
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
|
||||
func isITypeInstr(m string) bool {
|
||||
switch m {
|
||||
case "ADDI", "ADDIW", "SLTI", "SLTIU", "XORI", "ORI", "ANDI", "JALR":
|
||||
|
||||
Reference in New Issue
Block a user