feat(arch): add the amd64 extended-instruction layer with BF16 and VP2INTERSECT
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package arch
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import (
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"encoding/hex"
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"strings"
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"testing"
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)
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// The BF16 and VP2INTERSECT encodings have no toolchain oracle: go tool asm
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// knows neither family. The golden words below are transcribed from the
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// Intel SDM instruction entries and cross-checked against binutils-gdb's own
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// assembler testsuite: every row marked "GNU" matches a vector in
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// gas/testsuite/gas/i386/avx512_bf16.d, avx512_bf16_vl.d or
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// x86-64-vp2intersect.d byte for byte, so no entry rests on transcription
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// alone. The GNU dumps print AT&T order (sources first, destination last),
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// which is the order the operands are built in here too.
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func amd64ExtInstr(t *testing.T, mnem string, class ExtOperandKind) ExtInstr {
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t.Helper()
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for _, in := range Extensions(AMD64) {
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if in.Name == mnem && amd64LengthClass(in.Bytes) == class {
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return in
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}
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}
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t.Fatalf("no extended %s encoding at the %s vector length", mnem, class)
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return ExtInstr{}
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}
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func TestAmd64ExtGoldenBytes(t *testing.T) {
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for _, tt := range []struct {
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name string
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mnem string
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ops []ExtOperand
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want string // hex, little-endian bytes in memory order
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GNU string // the matching binutils-gdb line, empty for a derived register form
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}{
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// AVX512-BF16, EVEX.NDS.F2.0F38.W0.
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{"vcvtne2ps2bf16 zmm", "VCVTNE2PS2BF16",
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[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtZmm(6)},
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"62f2574872f4", "62 f2 57 48 72 f4 vcvtne2ps2bf16 %zmm4,%zmm5,%zmm6"},
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{"vcvtne2ps2bf16 ymm", "VCVTNE2PS2BF16",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f2572872f4", "62 f2 57 28 72 f4 vcvtne2ps2bf16 %ymm4,%ymm5,%ymm6"},
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{"vcvtne2ps2bf16 xmm", "VCVTNE2PS2BF16",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f2570872f4", "62 f2 57 08 72 f4 vcvtne2ps2bf16 %xmm4,%xmm5,%xmm6"},
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{"vcvtneps2bf16 zmm to ymm", "VCVTNEPS2BF16",
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[]ExtOperand{ExtZmm(5), ExtYmm(6)},
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"62f27e4872f5", "62 f2 7e 48 72 f5 vcvtneps2bf16 %zmm5,%ymm6"},
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{"vcvtneps2bf16 ymm to xmm", "VCVTNEPS2BF16",
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[]ExtOperand{ExtYmm(5), ExtXmm(6)},
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"62f27e2872f5", "62 f2 7e 28 72 f5 vcvtneps2bf16 %ymm5,%xmm6"},
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{"vcvtneps2bf16 xmm to xmm", "VCVTNEPS2BF16",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f27e0872f5", "62 f2 7e 08 72 f5 vcvtneps2bf16 %xmm5,%xmm6"},
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{"vdpbf16ps zmm", "VDPBF16PS",
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[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtZmm(6)},
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"62f2564852f4", "62 f2 56 48 52 f4 vdpbf16ps %zmm4,%zmm5,%zmm6"},
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{"vdpbf16ps ymm", "VDPBF16PS",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f2562852f4", "62 f2 56 28 52 f4 vdpbf16ps %ymm4,%ymm5,%ymm6"},
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{"vdpbf16ps xmm", "VDPBF16PS",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f2560852f4", "62 f2 56 08 52 f4 vdpbf16ps %xmm4,%xmm5,%xmm6"},
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// AVX512-VP2INTERSECT, EVEX.NDS.F2.0F38. The mask destination is
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// the ModR/M reg field, so a k register above k7 must refuse.
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{"vp2intersectd zmm k0", "VP2INTERSECTD",
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[]ExtOperand{ExtZmm(2), ExtZmm(1), ExtMask(0)},
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"62f26f4868c1", "62 f2 6f 48 68 c1 vp2intersectd %zmm1,%zmm2,%k0"},
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{"vp2intersectd ymm k2", "VP2INTERSECTD",
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[]ExtOperand{ExtYmm(2), ExtYmm(1), ExtMask(2)},
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"62f26f2868d1", "62 f2 6f 28 68 d1 vp2intersectd %ymm1,%ymm2,%k2"},
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{"vp2intersectd xmm k4", "VP2INTERSECTD",
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[]ExtOperand{ExtXmm(2), ExtXmm(1), ExtMask(4)},
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"62f26f0868e1", "62 f2 6f 08 68 e1 vp2intersectd %xmm1,%xmm2,%k4"},
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{"vp2intersectq zmm k0", "VP2INTERSECTQ",
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[]ExtOperand{ExtZmm(2), ExtZmm(1), ExtMask(0)},
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"62f2ef4868c1", "62 f2 ef 48 68 c1 vp2intersectq %zmm1,%zmm2,%k0"},
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{"vp2intersectq ymm k2", "VP2INTERSECTQ",
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[]ExtOperand{ExtYmm(2), ExtYmm(1), ExtMask(2)},
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"62f2ef2868d1", "62 f2 ef 28 68 d1 vp2intersectq %ymm1,%ymm2,%k2"},
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{"vp2intersectq xmm k4", "VP2INTERSECTQ",
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[]ExtOperand{ExtXmm(2), ExtXmm(1), ExtMask(4)},
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"62f2ef0868e1", "62 f2 ef 08 68 e1 vp2intersectq %xmm1,%xmm2,%k4"},
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// High registers exercise the EVEX extension bits: with both source
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// registers above 15 the B bar and X bar bits clear, while the
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// destination zmm23 keeps R bar set in byte one (derived from the
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// proven class above).
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{"vcvtne2ps2bf16 high registers", "VCVTNE2PS2BF16",
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[]ExtOperand{ExtZmm(21), ExtZmm(20), ExtZmm(23)},
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"62a2574072fc", ""},
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} {
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in := amd64ExtInstr(t, tt.mnem, operandClass(t, tt.ops))
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got, err := in.Encode(tt.ops)
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if err != nil {
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t.Errorf("%s: encode: %v", tt.name, err)
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continue
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}
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if hex.EncodeToString(got) != tt.want {
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t.Errorf("%s:\n got %x\n want %s", tt.name, got, tt.want)
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}
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}
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}
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// operandClass names the vector class a golden row exercises, the key the
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// helper resolves the table entry with. A row without a vector operand
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// (none today) would have nowhere to go.
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func operandClass(t *testing.T, ops []ExtOperand) ExtOperandKind {
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t.Helper()
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for _, op := range ops {
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switch op.Kind {
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case ExtXMM, ExtYMM, ExtZMM:
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return op.Kind
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}
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}
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t.Fatal("the golden row carries no vector operand to pick the entry with")
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return ExtXMM
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}
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// TestAmd64ExtTemplateIntegrity checks the metadata contract: every entry
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// names its manual reference, summary and feature, and every template carries
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// the fixed shape of an EVEX register form with the register-derived bits
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// zero, so a slip in the table is an error and not a stray byte.
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func TestAmd64ExtTemplateIntegrity(t *testing.T) {
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features := map[ExtFeature]bool{
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ExtFeatureBF16: true,
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ExtFeatureVP2INTERSECT: true,
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}
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for _, in := range Extensions(AMD64) {
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if in.Name == "" || in.Summary == "" || in.Ref == "" {
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t.Errorf("%+v: name, summary and reference are mandatory", in)
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}
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if !features[in.Feature] {
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t.Errorf("%s: feature %q is not an amd64 extension feature", in.Name, in.Feature)
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}
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if len(in.Bytes) != 6 {
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t.Errorf("%s: the template is %d bytes, want the 6-byte EVEX register form", in.Name, len(in.Bytes))
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continue
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}
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if in.Bytes[0] != 0x62 {
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t.Errorf("%s: the template opens with %02x, want the EVEX escape 62", in.Name, in.Bytes[0])
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}
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if in.Bytes[1]&0xf0 != 0 {
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t.Errorf("%s: byte one carries register bits %04b, want them zero", in.Name, in.Bytes[1]>>4)
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}
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if in.Bytes[2]&0x78 != 0 {
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t.Errorf("%s: byte two carries vvvv bits %04b, want them zero", in.Name, in.Bytes[2]>>3&0xf)
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}
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if in.Bytes[2]&0x04 == 0 {
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t.Errorf("%s: byte two lacks the reserved one-bit", in.Name)
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}
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if in.Bytes[3]&0x9f != 0 {
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t.Errorf("%s: byte three carries z, b, V prime or aaa bits, want them zero: %08b", in.Name, in.Bytes[3])
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}
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if in.Bytes[5]&0x3f != 0 || in.Bytes[5]&0xc0 != 0xc0 {
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t.Errorf("%s: byte five is %08b, want mod 11 with the reg and rm fields zero", in.Name, in.Bytes[5])
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}
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if in.Form.Arity() < 2 || in.Form.Arity() > 3 {
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t.Errorf("%s: form %s carries an unusable arity %d", in.Name, in.Form, in.Form.Arity())
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}
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}
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}
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// TestAmd64ExtEveryEntryCarriesGoldenVector pins the measure the layer is
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// judged by: every registered entry is covered by at least one golden vector
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// in the byte test above, so an entry without provenance cannot hide.
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func TestAmd64ExtEveryEntryCarriesGoldenVector(t *testing.T) {
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covered := map[string]bool{}
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for _, in := range Extensions(AMD64) {
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covered[in.Name+"|"+string(amd64LengthClass(in.Bytes))] = false
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}
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for _, tt := range []struct {
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mnem string
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class ExtOperandKind
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}{
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{"VCVTNE2PS2BF16", ExtZMM}, {"VCVTNE2PS2BF16", ExtYMM}, {"VCVTNE2PS2BF16", ExtXMM},
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{"VCVTNEPS2BF16", ExtZMM}, {"VCVTNEPS2BF16", ExtYMM}, {"VCVTNEPS2BF16", ExtXMM},
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{"VDPBF16PS", ExtZMM}, {"VDPBF16PS", ExtYMM}, {"VDPBF16PS", ExtXMM},
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{"VP2INTERSECTD", ExtZMM}, {"VP2INTERSECTD", ExtYMM}, {"VP2INTERSECTD", ExtXMM},
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{"VP2INTERSECTQ", ExtZMM}, {"VP2INTERSECTQ", ExtYMM}, {"VP2INTERSECTQ", ExtXMM},
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} {
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key := tt.mnem + "|" + string(tt.class)
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if _, ok := covered[key]; !ok {
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t.Errorf("the golden list covers %s, but the table registers no such entry", key)
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continue
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}
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covered[key] = true
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}
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for key, ok := range covered {
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if !ok {
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t.Errorf("%s has no golden vector", key)
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}
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}
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}
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func TestAmd64ExtRejects(t *testing.T) {
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for _, tt := range []struct {
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name string
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mnem string
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ops []ExtOperand
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quote string // a fragment the error carries
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}{
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{"wrong vector class", "VCVTNE2PS2BF16",
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[]ExtOperand{ExtZmm(1), ExtZmm(2), ExtYmm(3)},
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"wants a ZMM register"},
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{"destination class is the source's on the narrow convert", "VCVTNEPS2BF16",
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[]ExtOperand{ExtZmm(1), ExtZmm(2)},
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"wants a YMM register"},
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{"vector in the mask position", "VP2INTERSECTD",
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[]ExtOperand{ExtZmm(1), ExtZmm(2), ExtZmm(3)},
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"wants an opmask register"},
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{"mask register beyond k7", "VP2INTERSECTD",
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[]ExtOperand{ExtZmm(1), ExtZmm(2), ExtMask(8)},
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"outside 0-7"},
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{"vector where the general register belongs", "VCVTNE2PS2BF16",
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[]ExtOperand{ExtGpr32(0), ExtZmm(2), ExtZmm(3)},
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"wants a ZMM register"},
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{"wrong arity", "VP2INTERSECTD",
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[]ExtOperand{ExtZmm(1), ExtZmm(2)},
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"takes 3 operands"},
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{"arm64 arrangement suffix", "VCVTNE2PS2BF16",
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[]ExtOperand{{Kind: ExtZMM, Reg: 1, Arr: ExtArrS}, ExtZmm(2), ExtZmm(3)},
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"arrangement"},
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{"predicate qualifier", "VCVTNEPS2BF16",
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[]ExtOperand{{Kind: ExtZMM, Reg: 1, Qual: ExtQualZeroing}, ExtZmm(2)},
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"predicate qualifier"},
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} {
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in := amd64ExtInstr(t, tt.mnem, operandClass(t, tt.ops))
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_, err := in.Encode(tt.ops)
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if err == nil {
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t.Errorf("%s: encode succeeded, want an error", tt.name)
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continue
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}
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if !strings.Contains(err.Error(), tt.quote) {
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t.Errorf("%s: error %q lacks %q", tt.name, err, tt.quote)
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}
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}
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}
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