fix(asm): scale the FLDPQ and FSTPQ pair offsets by sixteen

The pair encoder derived the imm7 divisor from the width suffix alone, so
the 128-bit FP pairs divided their offsets by eight and encoded twice the
distance.  The Q spellings scale by sixteen like every other 128-bit
access; the differential kernel carries them now.

Assisted-by: GLM 5.3 Flash

asm/arm64_assemble.go

@@ -3147,8 +3147,11 @@ func encodeARM64Pair(mnem string, baseOp uint32, ops []*ast.Operand, fi arm64Fra
 		return nil, fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
 	}
 	scale := int64(8)
-	if strings.HasSuffix(mnem, "W") {
-		scale = 4
+	switch {
+	case strings.HasSuffix(mnem, "W"):
+		scale = 4 // the 32-bit pairs, signed and unsigned
+	case strings.HasSuffix(mnem, "Q"):
+		scale = 16 // the 128-bit FP pairs
 	}
 	load := strings.Contains(mnem, "LDP")
 	memOp, pairOp := ops[0], ops[1]