fix(asm): scale the FLDPQ and FSTPQ pair offsets by sixteen

The pair encoder derived the imm7 divisor from the width suffix alone, so
the 128-bit FP pairs divided their offsets by eight and encoded twice the
distance.  The Q spellings scale by sixteen like every other 128-bit
access; the differential kernel carries them now.

Assisted-by: GLM 5.3 Flash

asm/arm64_encode_test.go

@@ -625,10 +625,12 @@ func TestArm64ADR(t *testing.T) {
 	}
 }
 
-// TestArm64PairLoadStore pins LDP/STP/LDPW/FLDPD/FSTPD.
+// TestArm64PairLoadStore pins LDP/STP/LDPW/FLDPD/FSTPD and the 128-bit FP
+// pairs, whose offsets scale by sixteen.
 func TestArm64PairLoadStore(t *testing.T) {
 	got := arm64Words(t, "\tSTP (R2, R3), 8(R5)\n\tLDP -8(R5), (R2, R3)\n\tLDPW 4(R0), (R1, R2)\n\tSTPW (R1, R2), 4(R0)\n"+
-		"\tFLDPD 8(R0), (F1, F2)\n\tFSTPD (F3, F4), -8(R5)\n")
+		"\tFLDPD 8(R0), (F1, F2)\n\tFSTPD (F3, F4), -8(R5)\n"+
+		"\tFLDPQ 16(R0), (F1, F2)\n\tFSTPQ (F1, F2), 16(R0)\n")
 	want := []uint32{
 		0xa9008ca2, // STP (R2, R3), 8(R5)
 		0xa97f8ca2, // LDP -8(R5), (R2, R3)
@@ -636,6 +638,8 @@ func TestArm64PairLoadStore(t *testing.T) {
 		0x29008801, // STPW (R1, R2), 4(R0)
 		0x6d408801, // FLDPD 8(R0), (F1, F2)
 		0x6d3f90a3, // FSTPD (F3, F4), -8(R5)
+		0xad408801, // FLDPQ 16(R0), (F1, F2)
+		0xad008801, // FSTPQ (F1, F2), 16(R0)
 		0xd65f03c0,
 	}
 	if len(got) != len(want) {