feat(arch): the SVE2.1 narrowing two-to-one family

Assisted-by: GLM 5.3 Flash

asm/arm64_ext_asm_test.go

@@ -745,6 +745,62 @@ func TestArm64AssembleExtensionGatherGolden(t *testing.T) {
 	}
 }
 
+// TestArm64AssembleExtensionStage4Golden drives the SVE2.1 narrowing
+// two-to-one family through the full assembler: corpus text in, corpus word
+// out, with the two width extensions the arch-level golden test pins.
+func TestArm64AssembleExtensionStage4Golden(t *testing.T) {
+	tests := []struct {
+		stmt string
+		want uint32
+	}{
+		{"ZADDHNB Z22.S, Z10.S, Z8.H", 0x45b66148},
+		{"ZADDHNT Z22.S, Z10.S, Z8.H", 0x45b66548},
+		{"ZRADDHNB Z22.S, Z10.S, Z8.H", 0x45b66948},
+		{"ZRADDHNT Z22.S, Z10.S, Z8.H", 0x45b66d48},
+		{"ZRSUBHNB Z22.S, Z10.S, Z8.H", 0x45b67948},
+		{"ZRSUBHNT Z22.S, Z10.S, Z8.H", 0x45b67d48},
+		{"ZSUBHNB Z22.S, Z10.S, Z8.H", 0x45b67148},
+		{"ZSUBHNT Z22.S, Z10.S, Z8.H", 0x45b67548},
+		{"ZADDHNB Z8.H, Z10.H, Z11.B", 0x4568614b},
+		{"ZSUBHNT Z26.D, Z4.D, Z13.S", 0x45fa748d},
+	}
+	for _, tt := range tests {
+		words := assembleArm64Words(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")
+		if len(words) != 2 {
+			t.Fatalf("%s: got %d words, want the statement and RET", tt.stmt, len(words))
+		}
+		if words[0] != tt.want {
+			t.Errorf("%s:\n  got  %08x\n  want %08x", tt.stmt, words[0], tt.want)
+		}
+		if words[1] != 0xd65f03c0 {
+			t.Errorf("%s: RET encoded %08x", tt.stmt, words[1])
+		}
+	}
+}
+
+// TestArm64AssembleExtensionStage4Refusals pins the diagnostics the
+// narrowing statements get from the layer: the arrangement pair the single
+// size field over-determines.
+func TestArm64AssembleExtensionStage4Refusals(t *testing.T) {
+	tests := []struct {
+		stmt string
+		want string
+	}{
+		{"ZADDHNB Z22.B, Z10.B, Z8.H", "want .H, .S or .D"},
+		{"ZADDHNB Z22.S, Z10.H, Z8.H", "must match"},
+		{"ZADDHNB Z22.S, Z10.S, Z8.S", "want .H"},
+		{"ZADDHNB Z22.D, Z10.D, Z8.H", "want .S"},
+		{"ZADDHNB Z22.Q, Z10.Q, Z8.D", "want .H, .S or .D"},
+		{"ZADDHNB Z22.S, Z10.S, Z8", "carries no arrangement suffix"},
+	}
+	for _, tt := range tests {
+		got := assembleArm64SrcError(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")
+		if !strings.Contains(got, tt.want) {
+			t.Errorf("%s: error %q does not name %q", tt.stmt, got, tt.want)
+		}
+	}
+}
+
 // TestArm64AssembleExtensionGatherRefusals pins the diagnostics the
 // gather/scatter statements get from the layer: the addressing-mode
 // mismatches, the locked list arrangements, the zeroing qualifier of the

asm/extension_test.go

@@ -273,6 +273,15 @@ func TestExtensionNamesARM64(t *testing.T) {
 		"ZZIP2",
 		"ZZIPQ1",
 		"ZZIPQ2",
+		// The stage-four families: the SVE2.1 narrowing two-to-one set.
+		"ZADDHNB",
+		"ZADDHNT",
+		"ZRADDHNB",
+		"ZRADDHNT",
+		"ZRSUBHNB",
+		"ZRSUBHNT",
+		"ZSUBHNB",
+		"ZSUBHNT",
 		// The stage-three families: the SVE2 crypto group, the predicate
 		// counters and loop terminators with the 32-bit while compares, and
 		// the reductions into a SIMD register.
@@ -385,7 +394,7 @@ func TestExtensionNamesARM64(t *testing.T) {
 	if strings.Join(got, ",") != strings.Join(want, ",") {
 		t.Errorf("ExtensionNames(ARM64) = %v, want %v", got, want)
 	}
-	if n := len(arch.Extensions(arch.ARM64)); n != 381 {
-		t.Errorf("the family registers %d instructions, want 381", n)
+	if n := len(arch.Extensions(arch.ARM64)); n != 389 {
+		t.Errorf("the family registers %d instructions, want 389", n)
 	}
 }