fix(asm): correct RISC-V operand order and complete RVC compression

Assisted-by: DeepSeek V4 Pro

CHANGELOG.md

@@ -46,6 +46,15 @@ Unreleased changes on the `development` branch.
   are populated from the recorded stack-adjustment and source-line data, and
   a byte-exact ground-truth test compares framed and leaf functions against
   `GOARCH=riscv64 go tool asm`.
+- **RISC-V operand ordering and RVC compression.**  R-type instructions now
+  take `rs2, rs1, rd` and I-type arithmetic instructions take `imm12, rs1,
+  rd`, matching the Go assembler's documented operand order (previously both
+  were reversed, so non-commutative R-type instructions such as `SUB` encoded
+  the wrong operation).  The two-operand ternary forms (`ADD rs2, rd`,
+  `ADDI $imm, rd`, `SLLI $shamt, rd`) are now accepted.  RVC compression is
+  completed for `C.ADDI16SP`, `C.SLLI`, `C.SRLI`, `C.SRAI`, `C.ANDI`,
+  `C.NOP`, `C.EBREAK`, `C.MV` (from `ADDI`/`ADD`) and the commutative
+  `AND`/`OR`/`XOR` forms; the byte-exact ground-truth test now covers these.
 - **Debugger watchpoint slots.**  `gasm debug`'s `watch` command always used
   hardware watchpoint slot 0, so a second `watch` call silently overwrote
   the first.  Watchpoint slots are now tracked in the `Session` (DR0–DR3);