fix(asm): correct RISC-V operand order and complete RVC compression

Assisted-by: DeepSeek V4 Pro

asm/riscv_encode.go

@@ -460,6 +460,12 @@ func rvcCI(funct3, rd uint32, imm uint32) uint16 {
 	return uint16((funct3 << 13) | ((imm>>5)&1)<<12 | (rd << 7) | (imm&0x1F)<<2 | 0x1)
 }
 
+// rvcSLLI encodes C.SLLI, which shares funct3=0 with C.ADDI but lives in the
+// op=10 quadrant (unlike C.ADDI's op=01).
+func rvcSLLI(rd, shamt uint32) uint16 {
+	return uint16(((shamt>>5)&1)<<12 | (rd << 7) | (shamt&0x1F)<<2 | 0x2)
+}
+
 // rvcLSP encodes a CI-type stack-relative load: C.LDSP (funct3=3) or
 // C.FLDSP (funct3=1).  offset is the full byte offset; the immediate bits
 // are interleaved per the RISC-V spec: [5:3|8:6].
@@ -535,3 +541,23 @@ func rvcCB(funct3, rs1 uint32, offset int32) uint16 {
 	offBits |= ((uoff >> 5) & 1) << 2   // bit 2 = offset[5]
 	return uint16((funct3 << 13) | offBits | (rs1 << 7) | 0x1)
 }
+
+// rvcCBShift encodes a CB-type shift/immediate compressed instruction
+// (C.SRLI, C.SRAI, C.ANDI).  rd is the 3-bit prime-register index; imm is
+// the 6-bit shamt/immediate; funct2 selects the operation (0=SRLI, 1=SRAI,
+// 2=ANDI).
+func rvcCBShift(funct2, rd, imm uint32) uint16 {
+	return uint16((0x4 << 13) | ((imm>>5)&1)<<12 | (funct2 << 10) | (rd << 7) | (imm&0x1F)<<2 | 0x1)
+}
+
+// rvcADDI16SP encodes C.ADDI16SP: ADDI rd, imm, rd for the stack pointer
+// with a 10-bit signed, 16-byte-scaled immediate.  imm is the raw byte
+// offset; the immediate bits are extracted in the order [9|4|6|8:7|5].
+func rvcADDI16SP(rd uint32, imm int32) uint16 {
+	u := uint32(imm)
+	packed := uint32(0)
+	for _, bit := range []uint{9, 4, 6, 8, 7, 5} {
+		packed = packed<<1 | (u>>bit)&1
+	}
+	return uint16((0x3 << 13) | ((packed>>5)&1)<<12 | (rd << 7) | (packed&0x1F)<<2 | 0x1)
+}