fix(asm): correct RISC-V operand order and complete RVC compression

Assisted-by: DeepSeek V4 Pro

asm/riscv_frame.go

@@ -112,9 +112,13 @@ func riscvReturn(fi riscvFrameInfo) []byte {
 }
 
 // riscvSPAdjust emits an ADDI rd, imm, rd for the stack pointer (rd = rs1 =
-// X2), compressed to C.ADDI when the immediate is a nonzero 6-bit signed
-// value.
+// X2), compressed to C.ADDI16SP when the immediate is a nonzero 16-byte
+// multiple, else C.ADDI when it fits 6-bit signed.
 func riscvSPAdjust(imm int32) []byte {
+	if imm != 0 && imm%16 == 0 && imm >= -512 && imm <= 511 {
+		c := rvcADDI16SP(2, imm)
+		return []byte{byte(c), byte(c >> 8)}
+	}
 	if riscvFitsCAddi(imm) {
 		c := rvcCI(0x0, 2, uint32(imm)&0x3F)
 		return []byte{byte(c), byte(c >> 8)}
@@ -149,6 +153,9 @@ func riscvReturnEpilogueLen(fi riscvFrameInfo) int {
 }
 
 func riscvSPAdjustLen(imm int32) int {
+	if imm != 0 && imm%16 == 0 && imm >= -512 && imm <= 511 {
+		return 2
+	}
 	if riscvFitsCAddi(imm) {
 		return 2
 	}