fix(asm): correct RISC-V operand order and complete RVC compression

Assisted-by: DeepSeek V4 Pro
2026-08-13 15:13:31 +02:00
parent b78b6c5004
commit 373c09f725
8 changed files with 212 additions and 77 deletions
@@ -0,0 +1,32 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+#include "textflag.h"
+
+TEXT ·shifts(SB), NOSPLIT, $0
+	SLLI $3, X10, X10
+	SRLI $2, X10, X10
+	SRAI $1, X10, X10
+	RET
+
+TEXT ·logic(SB), NOSPLIT, $0
+	AND X11, X10, X10
+	OR X11, X10, X10
+	XOR X11, X10, X10
+	ANDI $7, X10, X10
+	RET
+
+TEXT ·mv(SB), NOSPLIT, $0
+	ADDI $0, X11, X10
+	RET
+
+TEXT ·nop(SB), NOSPLIT, $0
+	ADDI $0, X0
+	RET
+
+TEXT ·bigframe(SB), NOSPLIT, $24-0
+	RET
+
+TEXT ·ebreak(SB), NOSPLIT, $0
+	EBREAK
+	RET