fix(disasm): drop the implicit GOARCH constraint the naming files carried
The names naming_amd64.go and naming_amd64_test.go carried the _amd64 filename suffix, which the go tool reads as an implicit GOARCH=amd64 build constraint: the tables disappeared from every non-amd64 build and the package failed to compile for arm64, riscv64 and loong64, the other three architectures the tool assembles. Renaming to amd64_naming.go removes the constraint; the module builds again for all four GOARCH values. Assisted-by: GLM 5.3
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@@ -0,0 +1,496 @@
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package disasm
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import "fmt"
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// golang.org/x/arch decodes a handful of amd64 opcode families to no error
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// and the degenerate zero instruction: no opcode, no operands, one byte.
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// GoSyntax then renders the placeholder "Op(0)", decorated with whatever
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// prefixes it saw, and reports a length of one. The families are the ADCX
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// and ADOX carry-propagation pair, RDSEED, RDPID, the WAITPKG trio TPAUSE,
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// UMONITOR and UMWAIT, and the ENDBR pair.
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//
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// nameAMD64Degenerate restores the names the Go toolchain itself carries
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// for these families. The toolchain's assembler test corpus
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// machine-checks the encodings (amd64enc.s's "ADCXL DX, DX // 660f38f6d2"
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// and its kin), and the spellings below are the corpus's own; the parity
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// fixtures pin every corpus row the table names, so a decoder bump that
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// changes a length or a register reading fails there rather than silently
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// moving the text. The table is keyed by the opcode pattern: legacy
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// prefixes, opcode bytes and the ModR/M shape, so it names every encoding
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// of a family, not only the corpus rows.
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// amd64GPRNames holds the Plan 9 spelling of the general-purpose registers
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// by index. The names are width-independent: the mnemonic's suffix carries
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// the size, so RDX reads DX in both ADCXL and ADCXQ.
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var amd64GPRNames = [16]string{
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"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI",
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"R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
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}
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// amd64Prefixes is the legacy prefix reading of one instruction: the
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// operand-size override, the rep and repne not-really-prefixes, and REX.
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// n is the number of bytes the prefixes consumed.
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type amd64Prefixes struct {
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osz bool // 66
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rep bool // f3
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repne bool // f2
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rexW, rexR, rexX, rexB bool
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n int
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}
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// scanAMD64Prefixes reads the legacy prefixes at the start of code. It
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// stops at the first byte that is not one, which is where the opcode
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// begins.
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func scanAMD64Prefixes(code []byte) (amd64Prefixes, bool) {
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var p amd64Prefixes
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for ; p.n < len(code); p.n++ {
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switch b := code[p.n]; {
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case b == 0x66:
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p.osz = true
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case b == 0xf3:
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p.rep = true
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case b == 0xf2:
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p.repne = true
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case b >= 0x40 && b <= 0x4f:
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p.rexW = b&0x8 != 0
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p.rexR = b&0x4 != 0
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p.rexX = b&0x2 != 0
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p.rexB = b&0x1 != 0
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default:
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return p, true
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}
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}
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return p, false // prefixes with no opcode behind them
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}
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// amd64RM is the ModR/M (and SIB) reading of one operand, in the shape the
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// named families use: one register or one memory reference, never an
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// immediate. n counts the ModR/M byte, an SIB byte and the displacement.
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type amd64RM struct {
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regForm bool // mod == 11: the operand is the r/m register
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reg int // reg field with REX.R applied
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rm int // r/m field with REX.B applied, register form
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base int // memory base register, -1 when absent
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index int // memory index register, -1 when absent
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scale int
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disp int32
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rip bool // mod == 00, r/m == 101: RIP-relative
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n int
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}
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// decodeAMD64RM reads the ModR/M byte at the start of code, with the SIB
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// byte and displacement that mod 00 and 01 may carry behind it. rexR,
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// rexX and rexB extend the register fields to R8 through R15.
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func decodeAMD64RM(code []byte, rexR, rexX, rexB bool) (amd64RM, bool) {
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if len(code) == 0 {
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return amd64RM{}, false
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}
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b := code[0]
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var rm amd64RM
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rm.n = 1
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rm.reg = int(b>>3) & 7
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if rexR {
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rm.reg += 8
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}
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mod := b >> 6
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rmb := int(b & 7)
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if mod == 3 {
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rm.regForm = true
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rm.rm = rmb
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if rexB {
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rm.rm += 8
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}
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return rm, true
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}
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rm.base, rm.index, rm.scale = -1, -1, 1
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switch rmb {
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case 4: // SIB byte follows
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if len(code) < rm.n+1 {
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return amd64RM{}, false
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}
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sib := code[rm.n]
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rm.n++
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rm.scale = 1 << (sib >> 6)
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idx := int(sib>>3) & 7
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if rexX {
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idx += 8
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}
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if idx%8 != 4 { // index 100 is the no-index encoding
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rm.index = idx
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}
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bs := int(sib & 7)
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if rexB {
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bs += 8
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}
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if mod == 0 && bs%8 == 5 {
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// base 101 with no displacement byte is disp32 alone
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} else {
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rm.base = bs
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}
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case 5:
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if mod == 0 {
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rm.rip = true
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} else {
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rm.base = rmb
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if rexB {
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rm.base += 8
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}
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}
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default:
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rm.base = rmb
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if rexB {
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rm.base += 8
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}
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}
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switch mod {
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case 1:
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if len(code) < rm.n+1 {
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return amd64RM{}, false
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}
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rm.disp = int32(int8(code[rm.n]))
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rm.n++
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case 2:
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if len(code) < rm.n+4 {
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return amd64RM{}, false
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}
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rm.disp = int32(uint32(code[rm.n]) | uint32(code[rm.n+1])<<8 |
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uint32(code[rm.n+2])<<16 | uint32(code[rm.n+3])<<24)
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rm.n += 4
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}
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return rm, true
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}
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// text renders the operand the way the GoSyntax renderer prints a memory
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// reference: the displacement in hex (a zero displacement printed as 0),
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// then the base, then the scaled index.
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func (rm amd64RM) text() string {
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if rm.regForm {
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return amd64GPRNames[rm.rm]
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}
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s := "0"
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if rm.disp != 0 {
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s = fmt.Sprintf("%#x", rm.disp)
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}
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if rm.rip {
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// The renderer names the instruction pointer IP in a memory
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// reference.
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return s + "(IP)"
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}
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if rm.base >= 0 {
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s += "(" + amd64GPRNames[rm.base] + ")"
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}
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if rm.index >= 0 {
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s += fmt.Sprintf("(%s*%d)", amd64GPRNames[rm.index], rm.scale)
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}
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return s
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}
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// nameAMD64Degenerate names an amd64 encoding the decoder returned as the
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// degenerate zero instruction. It reports the rendered text, the
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// instruction's length in bytes and whether the bytes matched a family.
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// Unmatched bytes keep the renderer's own placeholder output.
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func nameAMD64Degenerate(code []byte) (string, int, bool) {
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p, ok := scanAMD64Prefixes(code)
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if !ok || len(code) < p.n+2 || code[p.n] != 0x0f {
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return "", 0, false
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}
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// UD1, the second undefined-instruction opcode: the toolchain's table
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// carries it with no operands, exactly two bytes, so the listing
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// consumes nothing behind them. Any bytes that follow belong to the
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// next instruction.
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if code[p.n+1] == 0xb9 &&
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!p.osz && !p.rep && !p.repne && !p.rexW && !p.rexR && !p.rexX && !p.rexB {
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return "UD1", p.n + 2, true
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}
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if len(code) < p.n+3 {
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return "", 0, false
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}
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tail := code[p.n+1:]
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switch tail[0] {
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case 0x38:
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return nameAMD64Carry(p, tail[1:])
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case 0xc7:
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return nameAMD64RNG(p, tail[1:])
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case 0xae:
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return nameAMD64Wait(p, tail[1:])
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case 0x1e:
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return nameAMD64Endbr(p, tail[1:])
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}
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return "", 0, false
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}
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// nameAMD64Carry names the ADCX and ADOX pair, 0F 38 F6 /r. The operand
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// size override carries ADCX and rep carries ADOX; the length suffix
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// follows REX.W. The destination is the reg field and the source the
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// r/m operand, printed source first.
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func nameAMD64Carry(p amd64Prefixes, tail []byte) (string, int, bool) {
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var name string
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switch {
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case p.osz && !p.rep && !p.repne:
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name = "ADCX"
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case p.rep && !p.osz && !p.repne:
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name = "ADOX"
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default:
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return "", 0, false
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}
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if len(tail) < 2 || tail[0] != 0xf6 {
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return "", 0, false
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}
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rm, ok := decodeAMD64RM(tail[1:], p.rexR, p.rexX, p.rexB)
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if !ok {
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return "", 0, false
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}
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suffix := "L"
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if p.rexW {
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suffix = "Q"
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}
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text := name + suffix + " " + rm.text() + ", " + amd64GPRNames[rm.reg]
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return text, p.n + 3 + rm.n, true
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}
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// nameAMD64RNG names RDSEED, 0F C7 /7, and its rep-prefixed sibling
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// RDPID. Both take the destination register in the r/m field and exist
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// only in the register form; the memory forms of the same opcode are
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// CLFLUSH and its descendants, which the decoder names itself. The size
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// suffix follows REX.W and the operand-size override.
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func nameAMD64RNG(p amd64Prefixes, tail []byte) (string, int, bool) {
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var name string
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switch {
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case p.rep && !p.osz && !p.repne:
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name = "RDPID"
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case !p.rep && !p.repne:
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name = "RDSEED"
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default:
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return "", 0, false
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}
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if len(tail) < 1 {
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return "", 0, false
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}
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rm, ok := decodeAMD64RM(tail, p.rexR, p.rexX, p.rexB)
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if !ok || !rm.regForm || rm.reg != 7 {
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return "", 0, false
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}
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if name == "RDPID" {
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return name + " " + amd64GPRNames[rm.rm], p.n + 2 + rm.n, true
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}
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suffix := "L"
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switch {
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case p.rexW:
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suffix = "Q"
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case p.osz:
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suffix = "W"
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}
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return name + suffix + " " + amd64GPRNames[rm.rm], p.n + 2 + rm.n, true
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}
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// nameAMD64Wait names the WAITPKG and monitor trio on 0F AE /6: TPAUSE
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// under the operand-size override, UMONITOR under rep and UMWAIT under
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// repne. Each takes one 32-bit register in the r/m field.
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func nameAMD64Wait(p amd64Prefixes, tail []byte) (string, int, bool) {
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var name string
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switch {
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case p.osz && !p.rep && !p.repne:
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name = "TPAUSE"
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case p.rep && !p.osz && !p.repne:
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name = "UMONITOR"
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case p.repne && !p.osz && !p.rep:
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name = "UMWAIT"
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default:
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return "", 0, false
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}
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if len(tail) < 1 {
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return "", 0, false
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}
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rm, ok := decodeAMD64RM(tail, p.rexR, p.rexX, p.rexB)
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if !ok || !rm.regForm || rm.reg != 6 {
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return "", 0, false
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}
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return name + " " + amd64GPRNames[rm.rm], p.n + 2 + rm.n, true
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}
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// nameAMD64Endbr names the ENDBR pair, F3 0F 1E with the fixed ModR/M
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// bytes FA for the 64-bit variant and FB for the 32-bit one. The
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// instructions take no operands.
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func nameAMD64Endbr(p amd64Prefixes, tail []byte) (string, int, bool) {
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if !p.rep || p.osz || p.repne {
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return "", 0, false
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}
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if len(tail) < 1 {
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return "", 0, false
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}
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switch tail[0] {
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case 0xfa:
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return "ENDBR64", p.n + 3, true
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case 0xfb:
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return "ENDBR32", p.n + 3, true
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}
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return "", 0, false
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}
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// nameAMD64Rejected names an amd64 encoding the decoder refuses outright,
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// one family at a time as the corpus rows land. Three kinds live here:
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// CLDEMOTE, NP 0F 1C /r with a memory operand, the toolchain's own table
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// being a memory-only instruction while the decoder rejects the encoding;
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// the register forms of the same opcode are the hint NOPs the corpus does
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// not spell, and they stay rejected. The 0F 01 pair CLAC/STAC and the
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// protection-key pair RDPKRU/WRPKRU, fixed three-byte encodings no ModR/M
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// shape distinguishes, which the decoder rejects although the corpus
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// assembles them. And the BMI1/BMI2 VEX families below.
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func nameAMD64Rejected(code []byte) (string, int, bool) {
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p, ok := scanAMD64Prefixes(code)
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if !ok || p.osz || p.rep || p.repne {
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return "", 0, false
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}
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if p.n == 0 && len(code) > 0 && code[0] == 0xc4 {
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return nameAMD64VEX(code)
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}
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if len(code) < p.n+3 || code[p.n] != 0x0f {
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return "", 0, false
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}
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switch code[p.n+1] {
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case 0x1c:
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rm, ok := decodeAMD64RM(code[p.n+2:], p.rexR, p.rexX, p.rexB)
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if !ok || rm.regForm {
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return "", 0, false
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}
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return "CLDEMOTE " + rm.text(), p.n + 2 + rm.n, true
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case 0x01:
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if !p.rexW && !p.rexR && !p.rexX && !p.rexB {
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switch code[p.n+2] {
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case 0xca:
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return "CLAC", p.n + 3, true
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case 0xcb:
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return "STAC", p.n + 3, true
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case 0xee:
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return "RDPKRU", p.n + 3, true
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case 0xef:
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return "WRPKRU", p.n + 3, true
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}
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}
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case 0xc7:
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// The error branch of the RDSEED family: the operand-size and
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// rep forms come back degenerate (handled above), while the
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// bare and REX-only forms are refused outright.
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if !p.rexR && !p.rexX {
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return nameAMD64RNG(p, code[p.n+2:])
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}
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}
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return "", 0, false
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}
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// amd64VEX is the reading of one three-byte VEX prefix, C4 rx bm wlpp.
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// REX extension, the escaped opcode map and the payload byte are decoded
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// once here; the families below are keyed on the pieces.
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type amd64VEX struct {
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r, x, b bool // register-extension bits, REX-style
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w bool // operand-width bit
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vvvv int // the inverted operand-register field
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l bool // vector-length bit, clear in every GPR family
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pp int // the legacy-prefix selector
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m int // the escaped opcode map, 2 for 0F38 and 3 for 0F3A
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n int // bytes consumed: C4 plus its two payload bytes
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}
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// parseAMD64VEX reads the C4 prefix at the start of code. A two-byte C5
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// VEX is not read: every corpus family here is three-byte.
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func parseAMD64VEX(code []byte) (amd64VEX, bool) {
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var v amd64VEX
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if len(code) < 4 || code[0] != 0xc4 {
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return v, false
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}
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b1, b2 := code[1], code[2]
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v.r = b1&0x80 == 0
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v.x = b1&0x40 == 0
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v.b = b1&0x20 == 0
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v.m = int(b1 & 0x1f)
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v.w = b2&0x80 != 0
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v.vvvv = int(^b2>>3) & 15
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v.l = b2&0x04 != 0
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v.pp = int(b2 & 0x03)
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v.n = 3
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return v, true
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}
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// nameAMD64VEX names the BMI1/BMI2 general-purpose VEX families the decoder
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// refuses with "unknown AVX Opcode". Every family is pinned to the prefix
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// selector, opcode map and operand arrangement the toolchain's corpus
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// carries; a byte pattern outside those (the vector-length bit set, a
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// different selector, a ModR/M reg field the family does not define) keeps
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// the placeholder.
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func nameAMD64VEX(code []byte) (string, int, bool) {
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v, ok := parseAMD64VEX(code)
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if !ok || v.l || v.m < 2 || v.m > 3 {
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return "", 0, false
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}
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opcode := code[v.n]
|
||||
rm, ok := decodeAMD64RM(code[v.n+1:], v.r, v.x, v.b)
|
||||
if !ok {
|
||||
return "", 0, false
|
||||
}
|
||||
suffix := "L"
|
||||
if v.w {
|
||||
suffix = "Q"
|
||||
}
|
||||
reg := amd64GPRNames[rm.reg]
|
||||
vvvv := amd64GPRNames[v.vvvv]
|
||||
|
||||
// Families on the 0F38 map.
|
||||
if v.m == 2 {
|
||||
switch {
|
||||
case opcode == 0xf2 && v.pp == 0x0:
|
||||
// ANDN rm, vvvv, reg.
|
||||
return "ANDN" + suffix + " " + rm.text() + ", " + vvvv + ", " + reg, v.n + 1 + rm.n, true
|
||||
case opcode == 0xf3 && v.pp == 0x0:
|
||||
// The three one-source pseudo-instructions share the
|
||||
// opcode: the ModR/M reg field selects the family.
|
||||
var name string
|
||||
switch rm.reg {
|
||||
case 1:
|
||||
name = "BLSR"
|
||||
case 2:
|
||||
name = "BLSMSK"
|
||||
case 3:
|
||||
name = "BLSI"
|
||||
}
|
||||
if name == "" {
|
||||
return "", 0, false
|
||||
}
|
||||
return name + suffix + " " + rm.text() + ", " + vvvv, v.n + 1 + rm.n, true
|
||||
case opcode == 0xf5 && v.pp == 0x0:
|
||||
// BZHI vvvv, rm, reg.
|
||||
return "BZHI" + suffix + " " + vvvv + ", " + rm.text() + ", " + reg, v.n + 1 + rm.n, true
|
||||
case opcode == 0xf6 && v.pp == 0x3:
|
||||
// MULX rm, vvvv, reg.
|
||||
return "MULX" + suffix + " " + rm.text() + ", " + vvvv + ", " + reg, v.n + 1 + rm.n, true
|
||||
case opcode == 0xf5 && v.pp == 0x3:
|
||||
// PDEP rm, vvvv, reg.
|
||||
return "PDEP" + suffix + " " + rm.text() + ", " + vvvv + ", " + reg, v.n + 1 + rm.n, true
|
||||
case opcode == 0xf5 && v.pp == 0x2:
|
||||
// PEXT rm, vvvv, reg.
|
||||
return "PEXT" + suffix + " " + rm.text() + ", " + vvvv + ", " + reg, v.n + 1 + rm.n, true
|
||||
case opcode == 0xf7 && v.pp == 0x0:
|
||||
// BEXTR vvvv, rm, reg.
|
||||
return "BEXTR" + suffix + " " + vvvv + ", " + rm.text() + ", " + reg, v.n + 1 + rm.n, true
|
||||
case opcode == 0xf7 && v.pp == 0x2:
|
||||
// SARX vvvv, rm, reg.
|
||||
return "SARX" + suffix + " " + vvvv + ", " + rm.text() + ", " + reg, v.n + 1 + rm.n, true
|
||||
case opcode == 0xf7 && v.pp == 0x1:
|
||||
// SHLX vvvv, rm, reg.
|
||||
return "SHLX" + suffix + " " + vvvv + ", " + rm.text() + ", " + reg, v.n + 1 + rm.n, true
|
||||
case opcode == 0xf7 && v.pp == 0x3:
|
||||
// SHRX vvvv, rm, reg.
|
||||
return "SHRX" + suffix + " " + vvvv + ", " + rm.text() + ", " + reg, v.n + 1 + rm.n, true
|
||||
}
|
||||
return "", 0, false
|
||||
}
|
||||
|
||||
// The 0F3A map: RORX $imm, rm, reg, with a dead vvvv field.
|
||||
if opcode == 0xf0 && v.pp == 0x3 && v.vvvv == 0 && v.n+1+rm.n < len(code) {
|
||||
imm := int8(code[v.n+1+rm.n])
|
||||
return fmt.Sprintf("RORX%s $%d, %s, %s", suffix, imm, rm.text(), reg), v.n + 2 + rm.n, true
|
||||
}
|
||||
return "", 0, false
|
||||
}
|
||||
Reference in new issue
Block a user