fix(asm): close the oracle parity gaps in frame addressing and calls

asm/riscv_assemble.go

@@ -162,6 +162,14 @@ func riscvInstrSize(instr *ast.Instr, fi riscvFrameInfo) int {
 		if isImmOperand(ops[0]) && ops[0].Imm.Sym == nil {
 			return riscvMovImmSize(regFromOperand(ops[1]), immFromOperand(ops[0]))
 		}
+		// Frame-relative loads and stores: a frame offset beyond the signed
+		// 12-bit range materialises the address in X31 first.
+		if isMemOperand(ops[0]) && !isMemOperand(ops[1]) {
+			return riscvFrameMemSize(ops[0], fi)
+		}
+		if isMemOperand(ops[1]) && !isMemOperand(ops[0]) {
+			return riscvFrameMemSize(ops[1], fi)
+		}
 	}
 	// I-type arithmetic with a large immediate expands to several instructions.
 	if (mnem == "ADDI" || mnem == "ANDI" || mnem == "ORI" || mnem == "XORI") && len(ops) >= 1 && isImmOperand(ops[0]) {
@@ -212,6 +220,14 @@ func encodeRISCVInstr(instr *ast.Instr, pc int, offsets map[string]int, fi riscv
 		// C.J, so always emit the 32-bit JAL.
 		var target string
 		if len(ops) >= 1 {
+			// JMP sym(SB): a tail call, JAL X0 against a symbol relocation.
+			if ops[0].Addr.Sym != nil && ops[0].Addr.Sym.Pseudo == "SB" {
+				if relocs != nil {
+					*relocs = append(*relocs, Reloc{Off: 0, After: 4, Name: ops[0].Addr.Sym.Name, Kind: RelRISCVJal, Addend: ops[0].Addr.Sym.Offset})
+				}
+				word = riscvJType(0, 0)
+				return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
+			}
 			target = labelFromOperand(ops[0])
 		}
 		targetOff, ok := offsets[target]
@@ -586,8 +602,7 @@ func encodeRISCVMov(instr *ast.Instr, fi riscvFrameInfo, relocs *[]Reloc) ([]byt
 		if rd < 0 || rs1 < 0 {
 			return nil, fmt.Errorf("MOV load: invalid operand")
 		}
-		word := riscvIType(riscvEnc{0x03, 0x3, 0x00}, rd, rs1, off)
-		return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
+		return riscvFrameMemOp(riscvEnc{0x03, 0x3, 0x00}, false, rd, rs1, off), nil
 	}
 
 	// Register → memory (store).
@@ -604,8 +619,7 @@ func encodeRISCVMov(instr *ast.Instr, fi riscvFrameInfo, relocs *[]Reloc) ([]byt
 		if rs2 < 0 || rs1 < 0 {
 			return nil, fmt.Errorf("MOV store: invalid operand")
 		}
-		word := riscvSType(riscvEnc{0x23, 0x3, 0x00}, rs1, rs2, off)
-		return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}, nil
+		return riscvFrameMemOp(riscvEnc{0x23, 0x3, 0x00}, true, rs2, rs1, off), nil
 	}
 
 	// Register → register (ADDI $0, src, dst).
@@ -620,6 +634,44 @@ func encodeRISCVMov(instr *ast.Instr, fi riscvFrameInfo, relocs *[]Reloc) ([]byt
 	}
 }
 
+// riscvFrameMemOp encodes a register-relative load (store=false, I-type
+// width 0x03) or store (store=true, S-type width 0x23) of the 64-bit width
+// at off(rs1).  Offsets beyond the signed 12-bit range materialise the
+// address in X31 first: LUI hi (the rounding split), then ADD X31, rs1,
+// matching the toolchain's large-frame addressing; the access uses the
+// sign-extended low part, which always fits.
+func riscvFrameMemOp(enc riscvEnc, store bool, reg, rs1 int, off int32) []byte {
+	if fits12(off) {
+		var word uint32
+		if store {
+			word = riscvSType(enc, rs1, reg, off)
+		} else {
+			word = riscvIType(enc, reg, rs1, off)
+		}
+		return []byte{byte(word), byte(word >> 8), byte(word >> 16), byte(word >> 24)}
+	}
+	lo := off - (splitHi(off) << 12)
+	out := riscvAddressInX31WithBase(off, rs1)
+	var word uint32
+	if store {
+		word = riscvSType(enc, 31, reg, lo)
+	} else {
+		word = riscvIType(enc, reg, 31, lo)
+	}
+	return append(out, wordLE(word)...)
+}
+
+// riscvFrameMemSize returns the encoded size of a frame-relative MOV for the
+// layout pass: 4 bytes when the offset fits, otherwise the X31
+// materialisation plus the access.
+func riscvFrameMemSize(op *ast.Operand, fi riscvFrameInfo) int {
+	rs1, off := memFromOperandWithFrame(op, fi)
+	if fits12(off) {
+		return 4
+	}
+	return len(riscvAddressInX31WithBase(off, rs1)) + 4
+}
+
 // encodeRISCVLoadImm encodes loading an immediate into a register (MOV $imm,
 // rd), matching the toolchain's instructionsForMOVConst.  For 12-bit
 // immediates it emits ADDI $imm, ZERO, rd (compressed to C.LI when it fits