feat(debug): instruction-level coverage and FP register display

Assisted-by: GLM 5.3 Flash

debug/display_linux_loong64.go

@@ -28,7 +28,11 @@ func printRegs(regs *Regs, codeBase, funcOff uint64) {
 }
 
 func printVectorRegs(v *VectorRegs) {
-	// No vector registers to display for loong64 yet.
+	fmt.Println("\n  FP registers (F0-F31):")
+	for i := 0; i < 32; i += 2 {
+		fmt.Printf("  F%-2d  = %#018x  F%-2d  = %#018x\n", i, v.F[i], i+1, v.F[i+1])
+	}
+	fmt.Printf("  FCC  = %#016x  FCSR = %#x\n", v.FCC, v.FCSR)
 }
 
 // archReturnAddr reads the return address from RA (loong64 convention).

debug/display_linux_riscv64.go

@@ -28,7 +28,11 @@ func printRegs(regs *Regs, codeBase, funcOff uint64) {
 }
 
 func printVectorRegs(v *VectorRegs) {
-	// No vector registers to display for riscv64 yet.
+	fmt.Println("\n  FP registers (F0-F31):")
+	for i := 0; i < 32; i += 2 {
+		fmt.Printf("  F%-2d  = %#018x  F%-2d  = %#018x\n", i, v.F[i], i+1, v.F[i+1])
+	}
+	fmt.Printf("  FCSR = %#x\n", v.FCSR)
 }
 
 // archReturnAddr reads the return address from RA (riscv64 convention).

debug/ptrace_linux_loong64.go

@@ -78,10 +78,20 @@ func (s *Session) GetFPRegs() (FPRegs, error) {
 	return fp, nil
 }
 
-// VectorRegs holds the LSX/LASX vector register state (placeholder).
-type VectorRegs struct{}
+// VectorRegs holds the FP register state shown by the regs command
+// (the scalar FP subset: 32 64-bit registers, fcc and fcsr; the LSX/LASX
+// vector files are not read yet).
+type VectorRegs struct {
+	F    [32]uint64
+	FCC  uint64
+	FCSR uint32
+}
 
-// GetVectorRegs retrieves the vector registers (not yet implemented for loong64).
+// GetVectorRegs retrieves the FP registers.
 func (s *Session) GetVectorRegs() (VectorRegs, error) {
-	return VectorRegs{}, nil
+	fp, err := s.GetFPRegs()
+	if err != nil {
+		return VectorRegs{}, err
+	}
+	return VectorRegs{F: fp.F, FCC: fp.FCC, FCSR: fp.FCSR}, nil
 }

debug/ptrace_linux_riscv64.go

@@ -76,10 +76,18 @@ func (s *Session) GetFPRegs() (FPRegs, error) {
 	return fp, nil
 }
 
-// VectorRegs holds the vector register state (placeholder).
-type VectorRegs struct{}
+// VectorRegs holds the FP register state shown by the regs command
+// (riscv64 has 32 64-bit FP registers and fcsr).
+type VectorRegs struct {
+	F    [32]uint64
+	FCSR uint32
+}
 
-// GetVectorRegs retrieves the vector registers (not yet implemented for riscv64).
+// GetVectorRegs retrieves the FP registers.
 func (s *Session) GetVectorRegs() (VectorRegs, error) {
-	return VectorRegs{}, nil
+	fp, err := s.GetFPRegs()
+	if err != nil {
+		return VectorRegs{}, err
+	}
+	return VectorRegs{F: fp.F, FCSR: fp.FCSR}, nil
 }