feat(debug): instruction-level coverage and FP register display

Assisted-by: GLM 5.3 Flash
2026-08-30 21:42:12 +02:00
parent 4171e412b5
commit 41b387e54d
7 changed files with 85 additions and 27 deletions
@@ -28,7 +28,11 @@ func printRegs(regs *Regs, codeBase, funcOff uint64) {
 }

 func printVectorRegs(v *VectorRegs) {
-	// No vector registers to display for riscv64 yet.
+	fmt.Println("\n  FP registers (F0-F31):")
+	for i := 0; i < 32; i += 2 {
+		fmt.Printf("  F%-2d  = %#018x  F%-2d  = %#018x\n", i, v.F[i], i+1, v.F[i+1])
+	}
+	fmt.Printf("  FCSR = %#x\n", v.FCSR)
 }

 // archReturnAddr reads the return address from RA (riscv64 convention).