feat(asm): add EVEX/AVX-512 encoding and assemble the AVX-512 kernel byte-identically

Assisted-by: Qwen 3.8 Max Preview

asm/encode.go

@@ -49,10 +49,11 @@ func (e *enc) encode(mnem string, ops []Operand) error {
 		return e.encodeJcc(cc, ops)
 	}
 
-	// VEX (AVX/AVX2) instructions: the trailing B/W/L/Q/D is part of the
-	// mnemonic, not a size suffix, so dispatch before splitSize.
-	if isVex(upper) {
-		return e.encodeVex(upper, ops)
+	// VEX (AVX/AVX2) and EVEX (AVX-512) instructions: the trailing
+	// B/W/L/Q/D is part of the mnemonic, not a size suffix, so dispatch
+	// before splitSize.
+	if isVex(upper) || isEvex(upper) || upper == "KMOVW" {
+		return e.encodeVec(upper, ops)
 	}
 
 	// CMOVcc and SETcc carry the condition in the mnemonic (CMOVLGT, SETNE).
@@ -114,6 +115,20 @@ func splitSize(upper string) (base string, size int) {
 	return upper, 0
 }
 
+// encodeVec dispatches a VEX/EVEX mnemonic to the right encoding: KMOVW has
+// its own direction-dependent opcodes; KTESTW is always VEX; everything else
+// takes EVEX when an operand demands it (a ZMM or K register, or an
+// EVEX-only mnemonic) and VEX otherwise.
+func (e *enc) encodeVec(upper string, ops []Operand) error {
+	if upper == "KMOVW" {
+		return e.encodeKmovw(ops)
+	}
+	if upper == "KTESTW" || !evexRequired(upper, ops) {
+		return e.encodeVex(upper, ops)
+	}
+	return e.encodeEvex(upper, ops)
+}
+
 // --- instruction components -------------------------------------------------
 
 type instr struct {