feat(parser): bracket register ranges, index-only VSIB and bare trailing immediates

Assisted-by: GLM 5.3 Flash

asm/assemble.go

@@ -846,6 +846,14 @@ func operandFromAST(op *ast.Operand, size int, fi frameInfo, link *linkInfo) (Op
 	case ast.OpAddr:
 		a := op.Addr
 
+		// A bracketed register range, [Z0-Z3]: the four-register source of
+		// the 4FMAPS/4VNNIW families.  The EVEX quad-register emit path
+		// needs an encoder operand of its own, so the shape stays a named
+		// gap rather than an encoding.
+		if a.Range != nil {
+			return nil, fmt.Errorf("register range %q needs quad-register encoder support", op.Raw)
+		}
+
 		// FP-relative: x+N(FP) → (N + fpAdjust)(SP).  The offset N lives in the
 		// symbol, not the address displacement.
 		if a.Sym != nil && a.Sym.Pseudo == "FP" {
@@ -893,6 +901,16 @@ func operandFromAST(op *ast.Operand, size int, fi frameInfo, link *linkInfo) (Op
 			}
 			return m, nil
 		}
+		// Index-only memory: the VSIB form the gather/scatter families
+		// read, 8(X4*1).  A scaled vector index addresses memory with no
+		// base register; the mod=00 SIB with base field 101 carries it.
+		if a.Index != "" {
+			idx, ok := ParseReg(a.Index)
+			if !ok {
+				return nil, fmt.Errorf("unknown index register %q", a.Index)
+			}
+			return Mem{Index: idx, Scale: a.Scale, Disp: a.Offset, HasIndex: true, Size: size}, nil
+		}
 		// Bare register.
 		if a.Sym != nil && a.Sym.Pseudo == "" && a.Sym.Name != "" {
 			if r, ok := ParseReg(a.Sym.Name); ok {