feat(parser): bracket register ranges, index-only VSIB and bare trailing immediates

Assisted-by: GLM 5.3 Flash

ast/ast.go

@@ -151,11 +151,21 @@ type Immediate struct {
 // Address is a non-immediate operand: a register, a memory reference, a symbol
 // reference or a label.  Fields are populated best-effort from the syntax.
 type Address struct {
-	Sym    *Symbol // name reference (bare ident, or name+off(pseudo))
-	Base   string  // base register, from (base)
-	Index  string  // index register, from (index*scale)
-	Scale  int     // index scale; 0 when absent
-	Offset int64   // leading displacement, from off(base)
-	HasOff bool    // a leading displacement is present
-	Shift  string  // verbatim arm64 shift suffix, e.g. "<< 2"
+	Sym    *Symbol   // name reference (bare ident, or name+off(pseudo))
+	Base   string    // base register, from (base)
+	Index  string    // index register, from (index*scale)
+	Scale  int       // index scale; 0 when absent
+	Offset int64     // leading displacement, from off(base)
+	HasOff bool      // a leading displacement is present
+	Shift  string    // verbatim arm64 shift suffix, e.g. "<< 2"
+	Range  *RegRange // bracketed register range; nil for every other form
+}
+
+// RegRange is a bracketed register range, [Z0-Z3]: the amd64 spelling of
+// the four-register source of the 4FMAPS/4VNNIW families.  Lo and Hi carry
+// the verbatim register spellings; the range is inclusive at both ends.
+type RegRange struct {
+	Lo  string
+	Hi  string
+	Pos token.Position
 }