feat(asm): assemble static symbols and the whole go-flac AVX2 kernel byte-identically

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docs/ARCHITECTURE.md

@@ -206,15 +206,21 @@ memory destination r/m), the direction-sensitive moves (`VMOVDQU`, `VMOVUPD`,
 `VMULPD`, `VXORPD`, `VUNPCKHPD`, the scalar `VADDSD`/`VMULSD`, `VCVTDQ2PD`,
 `VFMADD231PD`) and the no-operand `VZEROUPPER` — together with `VPERMD` and
 the scalar families (`CMOVcc`, `SETcc`, `LZCNT`/`TZCNT`, the extending moves,
-`CVTSx2SD`, `IMUL3`), covering every instruction the go-flac AVX2 kernels use
-apart from global-symbol loads.  Every encoding is validated two ways: by
-round-trip decoding through `golang.org/x/arch`, and byte-for-byte against the
-machine code the real Go assembler emits — a comparison that now holds for
-whole functions: every kernel function that avoids `SB` operands assembles to
-exactly the Go toolchain's bytes.  This increment covers register / memory /
-immediate / FP-frame operands, local-label jumps and these VEX SIMD forms;
-EVEX / AVX-512, `SB` (global symbol) operands (relocations) and object-file
-emission are the rest of Phase 2.
+`CVTSx2SD`, `IMUL3`), covering every instruction the go-flac AVX2 kernels
+use.  Every encoding is validated two ways: by round-trip decoding through
+`golang.org/x/arch`, and byte-for-byte against the machine code the real Go
+assembler emits — a comparison that holds for the whole kernel: all 17
+functions of the go-flac AVX2 file assemble to exactly the Go toolchain's
+bytes, the lone exception being the displacements of the static-constant
+loads, which the Go linker fills at link time.
+
+File-level assembly (`AssembleFile`) goes beyond single functions: it
+materialises the file's static symbols (`GLOBL`/`DATA`) in a data section
+behind the code and resolves references to them (`mask<>(SB)`) to
+RIP-relative loads whose displacements point inside the resulting image, so
+the bytes are self-consistent at any base address.  External (non-file-local)
+symbols are rejected: they need object-file emission, which — together with
+EVEX / AVX-512 and the other architectures — is the rest of Phase 2.
 
 ## Extension points