diff --git a/asm/amd64_families.go b/asm/amd64_families.go
index b537a17..5cdbcd8 100644
--- a/asm/amd64_families.go
+++ b/asm/amd64_families.go
@@ -19,6 +19,9 @@ func (e *enc) encodeAmd64Family(upper string, ops []Operand) (bool, error) {
 	if ok, err := e.encodeXsave(upper, ops); ok {
 		return true, err
 	}
+	if ok, err := e.encodeSSEMore(upper, ops); ok {
+		return true, err
+	}
 	return false, nil
 }
 
@@ -91,6 +94,9 @@ func amd64FamilyEncodable(upper string) bool {
 	if upper == "CMPXCHG8B" || upper == "CMPXCHG16B" {
 		return true
 	}
+	if upper == "INVPCID" || upper == "XABORT" {
+		return true
+	}
 	if _, ok := xsaveTable[upper]; ok {
 		return true
 	}
@@ -99,5 +105,18 @@ func amd64FamilyEncodable(upper string) bool {
 			return true
 		}
 	}
+	switch upper {
+	case "EMMS", "PSHUFW", "PSLLO", "PSRLO", "PMOVMSKB", "MOVQOZX", "MOVZWW", "MOVSWW":
+		return true
+	}
+	if _, ok := sseMaskmov[upper]; ok {
+		return true
+	}
+	if _, ok := mmxShiftImm[upper]; ok {
+		return true
+	}
+	if _, ok := mmxShiftVar[upper]; ok {
+		return true
+	}
 	return false
 }
diff --git a/asm/amd64_sse.go b/asm/amd64_sse.go
new file mode 100644
index 0000000..a0a13b1
--- /dev/null
+++ b/asm/amd64_sse.go
@@ -0,0 +1,566 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+package asm
+
+import "fmt"
+
+// This file implements the amd64 SIMD pieces the main tables lack: the MMX
+// bank glue (EMMS, the masked stores, the MMX shifts and shuffle, the
+// byte-mask extract), the MOVQ bank crossings' odd spellings and the leaf
+// aliases.  Every encoding here is pinned byte for byte against go tool asm
+// through the corpus lines in amd64_sse_test.go.
+
+// sseMaskmov maps the masked cache-line stores to their prefix and opcode:
+// OP src, dst with the second operand in the reg field, no memory operand.
+var sseMaskmov = map[string]sseBin{
+	"MASKMOVQ":  {0, 0xF7, false},
+	"MASKMOVOU": {0x66, 0xF7, false},
+}
+
+// sseMoreBin maps the packed and scalar legacy binaries the main table
+// lacks, reg = destination and r/m = source: the float comparisons, square
+// roots and reciprocal estimates, the SSE3 horizontal arithmetic, the SSE4.1
+// packed integers and the SSSE3 sign and horizontal ops.  The MMX twins of
+// the 0x66-prefixed members drop the prefix in the shared encoder.
+var sseMoreBin = map[string]sseBin{
+	"COMISS":     {0, 0x2F, false},
+	"UCOMISS":    {0, 0x2E, false},
+	"UCOMISD":    {0x66, 0x2E, false},
+	"SQRTPS":     {0, 0x51, false},
+	"SQRTPD":     {0x66, 0x51, false},
+	"SQRTSS":     {0xF3, 0x51, false},
+	"RCPPS":      {0, 0x53, false},
+	"RCPSS":      {0xF3, 0x53, false},
+	"RSQRTPS":    {0, 0x52, false},
+	"RSQRTSS":    {0xF3, 0x52, false},
+	"ADDSUBPD":   {0x66, 0xD0, false},
+	"ADDSUBPS":   {0xF2, 0xD0, false},
+	"HADDPD":     {0x66, 0x7C, false},
+	"HADDPS":     {0xF2, 0x7C, false},
+	"HSUBPD":     {0x66, 0x7D, false},
+	"HSUBPS":     {0xF2, 0x7D, false},
+	"MOVDDUP":    {0xF2, 0x12, false},
+	"MOVSHDUP":   {0xF3, 0x16, false},
+	"MOVSLDUP":   {0xF3, 0x12, false},
+	"LDDQU":      {0xF2, 0xF0, false},
+	"MOVNTDQA":   {0x66, 0x2A, true},
+	"PTEST":      {0x66, 0x17, true},
+	"PABSB":      {0x66, 0x1C, true},
+	"PABSW":      {0x66, 0x1D, true},
+	"PABSD":      {0x66, 0x1E, true},
+	"PACKSSWB":   {0x66, 0x63, false},
+	"PACKUSWB":   {0x66, 0x67, false},
+	"PACKSSLW":   {0x66, 0x6B, false},
+	"PACKUSDW":   {0x66, 0x2B, true},
+	"PADDSB":     {0x66, 0xEC, false},
+	"PADDSW":     {0x66, 0xED, false},
+	"PADDUSB":    {0x66, 0xDC, false},
+	"PADDUSW":    {0x66, 0xDD, false},
+	"PAVGB":      {0x66, 0xE0, false},
+	"PAVGW":      {0x66, 0xE3, false},
+	"PCMPEQQ":    {0x66, 0x29, true},
+	"PCMPGTQ":    {0x66, 0x37, true},
+	"PHADDW":     {0x66, 0x01, true},
+	"PHADDD":     {0x66, 0x02, true},
+	"PHADDSW":    {0x66, 0x03, true},
+	"PHSUBW":     {0x66, 0x05, true},
+	"PHSUBD":     {0x66, 0x06, true},
+	"PHSUBSW":    {0x66, 0x07, true},
+	"PHMINPOSUW": {0x66, 0x41, true},
+	"PMADDUBSW":  {0x66, 0x04, true},
+	"PMADDWL":    {0x66, 0xF5, false},
+	"PMAXSB":     {0x66, 0x3C, true},
+	"PMAXSD":     {0x66, 0x3D, true},
+	"PMAXSW":     {0x66, 0xEE, false},
+	"PMAXUB":     {0x66, 0xDE, false},
+	"PMAXUD":     {0x66, 0x3F, true},
+	"PMAXUW":     {0x66, 0x3E, true},
+	"PMINSB":     {0x66, 0x38, true},
+	"PMINSD":     {0x66, 0x39, true},
+	"PMINSW":     {0x66, 0xEA, false},
+	"PMINUB":     {0x66, 0xDA, false},
+	"PMINUD":     {0x66, 0x3B, true},
+	"PMINUW":     {0x66, 0x3A, true},
+	"PMULDQ":     {0x66, 0x28, true},
+	"PMULLD":     {0x66, 0x40, true},
+	"PMULHRSW":   {0x66, 0x0B, true},
+	"PMULHUW":    {0x66, 0xE4, false},
+	"PMULHW":     {0x66, 0xE5, false},
+	"PMULLW":     {0x66, 0xD5, false},
+	"PMULULQ":    {0x66, 0xF4, false},
+	"PCMPGTL":    {0x66, 0x66, false},
+	"PMOVSXBD":   {0x66, 0x21, true},
+	"PMOVSXBQ":   {0x66, 0x22, true},
+	"PMOVSXBW":   {0x66, 0x20, true},
+	"PMOVSXDQ":   {0x66, 0x25, true},
+	"PMOVSXWD":   {0x66, 0x23, true},
+	"PMOVSXWQ":   {0x66, 0x24, true},
+	"PMOVZXBD":   {0x66, 0x31, true},
+	"PMOVZXBQ":   {0x66, 0x32, true},
+	"PMOVZXBW":   {0x66, 0x30, true},
+	"PMOVZXDQ":   {0x66, 0x35, true},
+	"PMOVZXWD":   {0x66, 0x33, true},
+	"PMOVZXWQ":   {0x66, 0x34, true},
+	// The conversion aliases the Plan 9 table spells with an L: the dword
+	// sources and destinations of the packed integer/float converts.
+	"CVTPL2PD":   {0xF3, 0xE6, false},
+	"CVTPL2PS":   {0, 0x5B, false},
+	"CVTPD2PL":   {0xF2, 0xE6, false},
+	"CVTPS2PL":   {0x66, 0x5B, false},
+	"CVTTPD2PL":  {0x66, 0xE6, false},
+	"CVTTPS2PL":  {0xF3, 0x5B, false},
+	"PSADBW":     {0x66, 0xF6, false},
+	"PSUBSB":     {0x66, 0xE8, false},
+	"PSUBSW":     {0x66, 0xE9, false},
+	"PSUBUSB":    {0x66, 0xD8, false},
+	"PSUBUSW":    {0x66, 0xD9, false},
+	"PSIGNB":     {0x66, 0x08, true},
+	"PSIGNW":     {0x66, 0x09, true},
+	"PSIGND":     {0x66, 0x0A, true},
+	"PUNPCKHBW":  {0x66, 0x68, false},
+	"PUNPCKHLQ":  {0x66, 0x6A, false},
+	"PUNPCKHQDQ": {0x66, 0x6D, false},
+	"PUNPCKHWL":  {0x66, 0x69, false},
+	"PUNPCKLLQ":  {0x66, 0x62, false},
+	"PUNPCKLQDQ": {0x66, 0x6C, false},
+	"PUNPCKLWL":  {0x66, 0x61, false},
+}
+
+// sseMoreImm3 maps the imm8-controlled three-operand instructions the main
+// table lacks: OP $imm, src, dst.
+var sseMoreImm3 = map[string]sseImm3{
+	"ROUNDPS":   {0x66, 0x08, true},
+	"ROUNDPD":   {0x66, 0x09, true},
+	"ROUNDSS":   {0x66, 0x0A, true},
+	"ROUNDSD":   {0x66, 0x0B, true},
+	"DPPS":      {0x66, 0x40, true},
+	"DPPD":      {0x66, 0x41, true},
+	"BLENDPS":   {0x66, 0x0C, true},
+	"BLENDPD":   {0x66, 0x0D, true},
+	"INSERTPS":  {0x66, 0x21, true},
+	"MPSADBW":   {0x66, 0x42, true},
+	"PCMPESTRM": {0x66, 0x60, true},
+	"PCMPESTRI": {0x66, 0x61, true},
+	"PCMPISTRM": {0x66, 0x62, true},
+	"PCMPISTRI": {0x66, 0x63, true},
+}
+
+// sseBlendv maps the variable blends whose implicit mask is X0: the first
+// operand must be the literal X0, the register the hardware reads.
+var sseBlendv = map[string]sseBin{
+	"BLENDVPS": {0x66, 0x14, true},
+	"BLENDVPD": {0x66, 0x15, true},
+	"PBLENDVB": {0x66, 0x10, true},
+}
+
+// sseHighLow maps the high/low half moves to their load/store opcode pair.
+// A memory source loads (reg = destination), a memory destination stores
+// (reg = the register source).
+var sseHighLow = map[string]sseMove{
+	"MOVHPD": {0x66, 0x16, 0x17},
+	"MOVHPS": {0, 0x16, 0x17},
+	"MOVLPD": {0x66, 0x12, 0x13},
+	"MOVLPS": {0, 0x12, 0x13},
+}
+
+// sseRegReg maps the register-to-register half moves, register destination
+// and register source alone: MOVHLPS and MOVLHPS.
+var sseRegReg = map[string]sseBin{
+	"MOVHLPS": {0, 0x12, false},
+	"MOVLHPS": {0, 0x16, false},
+}
+
+// sseMovmsk maps the sign-mask extractions to a GPR: OP vec, gpr.
+var sseMovmsk = map[string]sseBin{
+	"MOVMSKPS": {0, 0x50, false},
+	"MOVMSKPD": {0x66, 0x50, false},
+}
+
+// sseMovnt maps the non-temporal stores, OP reg, mem, plus MOVNTDQA's load
+// (which rides sseMoreBin).
+var sseMovnt = map[string]sseBin{
+	"MOVNTPS": {0, 0x2B, false},
+	"MOVNTPD": {0x66, 0x2B, false},
+	"MOVNTQ":  {0, 0xE7, false},
+	"MOVNTO":  {0x66, 0xE7, false},
+	"MOVNTIL": {0, 0xC3, false},
+	"MOVNTIQ": {0, 0xC3, false},
+}
+
+// mmxShiftImm lists the packed integer shifts whose immediate form the MMX
+// bank spells without the 0x66 prefix; the digit rides the 0F 71/72/73
+// group, the same /digits the XMM forms carry.
+var mmxShiftImm = map[string]sseShift{
+	"PSLLW": {0x71, 6},
+	"PSRLW": {0x71, 2},
+	"PSRAW": {0x71, 4},
+	"PSLLL": {0x72, 6},
+	"PSRLL": {0x72, 2},
+	"PSRAL": {0x72, 4},
+	"PSLLQ": {0x73, 6},
+	"PSRLQ": {0x73, 2},
+}
+
+// mmxShiftVar lists the variable-count forms over the MMX bank, the same
+// opcodes the XMM variable shifts ride, prefix dropped.
+var mmxShiftVar = map[string]byte{
+	"PSLLW": 0xF1,
+	"PSRLW": 0xD1,
+	"PSRAW": 0xE1,
+	"PSLLL": 0xF2,
+	"PSRLL": 0xD2,
+	"PSRAL": 0xE2,
+	"PSLLQ": 0xF3,
+	"PSRLQ": 0xD3,
+}
+
+// sseOctaShift lists the octa byte shifts' extra spellings: PSLLO and PSRLO
+// are the Plan 9 names of PSLLDQ/PSRLDQ, XMM only.
+var sseOctaShift = map[string]sseShift{
+	"PSLLO": {0x73, 7},
+	"PSRLO": {0x73, 3},
+}
+
+// isMmx reports whether the operand is an MMX register.
+func isMmx(op Operand) bool {
+	r, ok := op.(Reg)
+	return ok && r.mmx
+}
+
+// encodeSSEMore encodes the MMX glue and the leaf SIMD spellings.  It
+// reports whether the mnemonic belongs to the layer; a false result hands
+// the mnemonic back to the caller.
+func (e *enc) encodeSSEMore(upper string, ops []Operand) (bool, error) {
+	if upper == "EMMS" {
+		if len(ops) != 0 {
+			return true, fmt.Errorf("EMMS takes no operands, got %d", len(ops))
+		}
+		return true, e.emit(&instr{opcode: []byte{0x0F, 0x77}, modrm: -1, sib: -1})
+	}
+	if m, ok := sseMaskmov[upper]; ok {
+		if len(ops) != 2 {
+			return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
+		}
+		srcReg, ok1 := ops[0].(Reg)
+		dstReg, ok2 := ops[1].(Reg)
+		if !ok1 || !ok2 || !srcReg.isVec() && !srcReg.mmx || !dstReg.isVec() && !dstReg.mmx {
+			return true, fmt.Errorf("%s takes two vector or MMX registers", upper)
+		}
+		i := &instr{prefix: m.prefix, opcode: []byte{0x0F, m.op}, modrm: -1, sib: -1}
+		if err := setRM(i, dstReg, srcReg, 8); err != nil {
+			return true, err
+		}
+		return true, e.emit(i)
+	}
+	// The packed shifts over the MMX bank drop the 0x66 prefix the XMM forms
+	// carry; only a shift name enters the MMX path, the XMM spellings of the
+	// shifts and every other packed binary fall through to the main tables.
+	if _, isShift := mmxShiftImm[upper]; isShift {
+		if e.encodeMmxShiftGate(ops) {
+			return e.encodeMmxShift(upper, ops)
+		}
+	} else if _, isVar := mmxShiftVar[upper]; isVar {
+		if e.encodeMmxShiftGate(ops) {
+			return e.encodeMmxShift(upper, ops)
+		}
+	}
+	// PSHUFW is the MMX word shuffle, 0F 70 with no prefix: the XMM twins
+	// (PSHUFD and friends) dispatch through the main shuffle table.
+	if upper == "PSHUFW" {
+		if len(ops) != 3 {
+			return true, fmt.Errorf("PSHUFW expects 3 operands ($imm, src, dst), got %d", len(ops))
+		}
+		imm, ok := ops[0].(Imm)
+		if !ok {
+			return true, fmt.Errorf("PSHUFW needs an imm8 first operand")
+		}
+		immByte, err := imm8(int64(imm))
+		if err != nil {
+			return true, err
+		}
+		dstReg, ok2 := ops[2].(Reg)
+		if !ok2 || !dstReg.mmx {
+			return true, fmt.Errorf("PSHUFW destination must be an MMX register")
+		}
+		i := &instr{opcode: []byte{0x0F, 0x70}, modrm: -1, sib: -1}
+		if err := setRM(i, dstReg, ops[1], 8); err != nil {
+			return true, err
+		}
+		i.imm = []byte{immByte}
+		return true, e.emit(i)
+	}
+	if spec, ok := sseOctaShift[upper]; ok {
+		return e.encodeMmxShiftForm(upper, spec, 0x66, ops)
+	}
+	// The byte-mask extract over the MMX bank rides the same 0F D7 opcode
+	// without the prefix; the XMM spelling falls through.
+	if upper == "PMOVMSKB" && len(ops) == 2 {
+		if srcReg, ok := ops[0].(Reg); ok && srcReg.mmx {
+			dstReg, ok2 := ops[1].(Reg)
+			if !ok2 || dstReg.isVec() || dstReg.mmx {
+				return true, fmt.Errorf("%s destination must be a general register", upper)
+			}
+			i := newInstr(4, []byte{0x0F, 0xD7})
+			if err := setRM(i, dstReg, srcReg, 4); err != nil {
+				return true, err
+			}
+			return true, e.emit(i)
+		}
+	}
+	// MOVQOZX is the octa-to-quad zero-extend load, F3 0F D6: an MMX or
+	// memory source into an XMM destination, the MOVQ2DQ opcode.
+	if upper == "MOVQOZX" {
+		if len(ops) != 2 {
+			return true, fmt.Errorf("MOVQOZX expects 2 operands, got %d", len(ops))
+		}
+		dstReg, ok := ops[1].(Reg)
+		if !ok || !dstReg.isVec() {
+			return true, fmt.Errorf("MOVQOZX destination must be an XMM register")
+		}
+		switch ops[0].(type) {
+		case Reg, Mem, sbMem:
+		default:
+			return true, fmt.Errorf("MOVQOZX source must be an MMX register or memory")
+		}
+		i := &instr{prefix: 0xF3, opcode: []byte{0x0F, 0xD6}, modrm: -1, sib: -1}
+		if err := setRM(i, dstReg, ops[0], 8); err != nil {
+			return true, err
+		}
+		return true, e.emit(i)
+	}
+	// MOVZWW and MOVSWW are the word zero/sign-extend moves under aliases:
+	// the MOVWLZX and MOVWLSX opcodes carrying the word width's 0x66 prefix.
+	switch upper {
+	case "MOVZWW", "MOVSWW":
+		op := []byte{0x0F, 0xB7}
+		if upper == "MOVSWW" {
+			op[1] = 0xBF
+		}
+		if len(ops) != 2 {
+			return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
+		}
+		dstReg, ok := ops[1].(Reg)
+		if !ok {
+			return true, fmt.Errorf("%s destination must be a register", upper)
+		}
+		i := newInstr(2, op)
+		if err := setRM(i, dstReg, ops[0], 2); err != nil {
+			return true, err
+		}
+		return true, e.emit(i)
+	}
+	// The packed and scalar binaries: reg = destination, r/m = source, the
+	// shared encoder carrying the MMX prefix drop.
+	if m, ok := sseMoreBin[upper]; ok {
+		return true, e.encodeSSEBin(m, ops)
+	}
+	// The imm8-controlled instructions: OP $imm, src, dst.
+	if m, ok := sseMoreImm3[upper]; ok {
+		return true, e.encodeSSEImm3(m, ops)
+	}
+	// The variable blends with their implicit X0 mask: the first operand is
+	// the literal X0, the register the encoding leaves out.
+	if m, ok := sseBlendv[upper]; ok {
+		if len(ops) != 3 {
+			return true, fmt.Errorf("%s expects 3 operands (X0, src, dst), got %d", upper, len(ops))
+		}
+		x0, ok := ops[0].(Reg)
+		if !ok || !x0.isVec() || x0.idx != 0 || x0.size != 16 {
+			return true, fmt.Errorf("%s first operand must be X0", upper)
+		}
+		return true, e.encodeSSEBin(m, ops[1:])
+	}
+	// The high/low half moves split by direction: a memory source loads, a
+	// memory destination stores, both two-operand.
+	if m, ok := sseHighLow[upper]; ok {
+		if len(ops) != 2 {
+			return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
+		}
+		srcReg, srcVec := vecReg(ops[0])
+		dstReg, dstVec := vecReg(ops[1])
+		var op byte
+		var reg Reg
+		var rm Operand
+		switch {
+		case srcVec && isX86Mem(ops[1]):
+			op, reg, rm = m.store, srcReg, ops[1]
+		case dstVec && isX86Mem(ops[0]):
+			op, reg, rm = m.load, dstReg, ops[0]
+		default:
+			return true, fmt.Errorf("%s takes one vector register and one memory operand", upper)
+		}
+		i := &instr{prefix: m.prefix, opcode: []byte{0x0F, op}, modrm: -1, sib: -1}
+		if err := setRM(i, reg, rm, 8); err != nil {
+			return true, err
+		}
+		return true, e.emit(i)
+	}
+	// The register-to-register half moves.
+	if m, ok := sseRegReg[upper]; ok {
+		if len(ops) != 2 {
+			return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
+		}
+		srcReg, srcVec := vecReg(ops[0])
+		dstReg, dstVec := vecReg(ops[1])
+		if !srcVec || !dstVec {
+			return true, fmt.Errorf("%s takes two XMM registers", upper)
+		}
+		i := &instr{opcode: []byte{0x0F, m.op}, modrm: -1, sib: -1}
+		if err := setRM(i, dstReg, srcReg, 8); err != nil {
+			return true, err
+		}
+		return true, e.emit(i)
+	}
+	// The sign-mask extractions: the vector source's sign bits pack into a
+	// general register.
+	if m, ok := sseMovmsk[upper]; ok {
+		if len(ops) != 2 {
+			return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
+		}
+		srcReg, srcVec := vecReg(ops[0])
+		dstReg, ok := ops[1].(Reg)
+		if !srcVec || !ok || dstReg.isVec() || dstReg.mmx {
+			return true, fmt.Errorf("%s takes a vector register and a general register", upper)
+		}
+		i := &instr{prefix: m.prefix, opcode: []byte{0x0F, m.op}, modrm: -1, sib: -1}
+		if err := setRM(i, dstReg, srcReg, 4); err != nil {
+			return true, err
+		}
+		return true, e.emit(i)
+	}
+	// The non-temporal stores: the register source rides reg, the memory
+	// destination r/m; MOVNTIL/IQ store from a general register and MOVNTIQ
+	// carries REX.W.
+	if m, ok := sseMovnt[upper]; ok {
+		if len(ops) != 2 {
+			return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
+		}
+		var srcReg Reg
+		switch r := ops[0].(type) {
+		case Reg:
+			if upper == "MOVNTIL" || upper == "MOVNTIQ" {
+				if r.isVec() || r.mmx {
+					return true, fmt.Errorf("%s source must be a general register", upper)
+				}
+				srcReg = r
+			} else {
+				if !r.isVec() && !r.mmx {
+					return true, fmt.Errorf("%s source must be a vector or MMX register", upper)
+				}
+				srcReg = r
+			}
+		default:
+			return true, fmt.Errorf("%s source must be a register", upper)
+		}
+		if !isX86Mem(ops[1]) {
+			return true, fmt.Errorf("%s destination must be memory", upper)
+		}
+		i := &instr{prefix: m.prefix, opcode: []byte{0x0F, m.op}, modrm: -1, sib: -1, rexW: upper == "MOVNTIQ"}
+		if err := setRM(i, srcReg, ops[1], 8); err != nil {
+			return true, err
+		}
+		return true, e.emit(i)
+	}
+	// EXTRACTPS is the lane extract to a GPR or memory, the PEXTR layout.
+	if upper == "EXTRACTPS" {
+		return true, e.encodeSSEExtract(sseExtract{op: []byte{0x0F, 0x3A, 0x17}}, ops)
+	}
+	// CVTSL2SS and CVTSQ2SS are the integer-to-scalar-single converts, the
+	// CVTSL2SD pair's F3 twin: F3 0F 2A with reg = XMM destination, REX.W
+	// on the quad source spelling.
+	if upper == "CVTSL2SS" || upper == "CVTSQ2SS" {
+		if len(ops) != 2 {
+			return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
+		}
+		dstReg, ok := ops[1].(Reg)
+		if !ok || !dstReg.isVec() {
+			return true, fmt.Errorf("%s destination must be a vector register", upper)
+		}
+		i := newInstr(0, []byte{0x0F, 0x2A})
+		i.rexW = upper == "CVTSQ2SS"
+		i.prefix = 0xF3
+		if err := setRM(i, dstReg, ops[0], 8); err != nil {
+			return true, err
+		}
+		return true, e.emit(i)
+	}
+	return false, nil
+}
+
+// encodeMmxShiftGate reports whether the shift's destination operand is an
+// MMX register, the case the bank's own prefix-free forms cover.
+func (e *enc) encodeMmxShiftGate(ops []Operand) bool {
+	if len(ops) != 2 {
+		return false
+	}
+	dstReg, ok := ops[1].(Reg)
+	return ok && dstReg.mmx
+}
+
+// encodeMmxShift routes the MMX shift between its immediate form
+// (OP $imm, dst, the 0F 71/72/73 /digit group) and its variable-count form
+// (OP count, dst, the 0F D1-F3 row).
+func (e *enc) encodeMmxShift(upper string, ops []Operand) (bool, error) {
+	if spec, ok := mmxShiftImm[upper]; ok {
+		if _, isImm := ops[0].(Imm); isImm {
+			if len(ops) != 2 {
+				return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
+			}
+			immByte, err := imm8(int64(ops[0].(Imm)))
+			if err != nil {
+				return true, err
+			}
+			i := &instr{opcode: []byte{0x0F, spec.op}, modrm: -1, sib: -1}
+			if err := setRMDigit(i, spec.digit, ops[1], 8); err != nil {
+				return true, err
+			}
+			i.imm = []byte{immByte}
+			return true, e.emit(i)
+		}
+	}
+	if op, ok := mmxShiftVar[upper]; ok {
+		if len(ops) != 2 {
+			return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
+		}
+		if !vecOrMem(ops[0]) && !isMmx(ops[0]) {
+			return true, fmt.Errorf("%s count must be an immediate, an MMX register or memory", upper)
+		}
+		dstReg, ok := ops[1].(Reg)
+		if !ok || !dstReg.mmx {
+			return true, fmt.Errorf("%s destination must be an MMX register", upper)
+		}
+		i := &instr{opcode: []byte{0x0F, op}, modrm: -1, sib: -1}
+		if err := setRM(i, dstReg, ops[0], 8); err != nil {
+			return true, err
+		}
+		return true, e.emit(i)
+	}
+	return true, fmt.Errorf("unsupported instruction %q", upper)
+}
+
+// encodeMmxShiftForm emits one XMM octa shift: OP $imm, dst, the 0x66
+// prefix carried.
+func (e *enc) encodeMmxShiftForm(upper string, spec sseShift, prefix byte, ops []Operand) (bool, error) {
+	if len(ops) != 2 {
+		return true, fmt.Errorf("%s expects 2 operands, got %d", upper, len(ops))
+	}
+	imm, ok := ops[0].(Imm)
+	if !ok {
+		return true, fmt.Errorf("%s needs an immediate count", upper)
+	}
+	immByte, err := imm8(int64(imm))
+	if err != nil {
+		return true, err
+	}
+	dstReg, ok2 := ops[1].(Reg)
+	if !ok2 || !dstReg.isVec() {
+		return true, fmt.Errorf("%s destination must be the second, vector operand", upper)
+	}
+	i := &instr{prefix: prefix, opcode: []byte{0x0F, spec.op}, modrm: -1, sib: -1}
+	if err := setRMDigit(i, spec.digit, dstReg, 8); err != nil {
+		return true, err
+	}
+	i.imm = []byte{immByte}
+	return true, e.emit(i)
+}
diff --git a/asm/amd64_sse_test.go b/asm/amd64_sse_test.go
new file mode 100644
index 0000000..c32161f
--- /dev/null
+++ b/asm/amd64_sse_test.go
@@ -0,0 +1,1497 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+package asm
+
+import "testing"
+
+// amd64SseCorpus holds every line the Go toolchain's own
+// amd64enc.s carries for the legacy SSE and MMX families and the MOVQ bank crossings, with the bytes go
+// tool asm emits for each: the differential ground truth the layer is
+// proven against, line for line.
+var amd64SseCorpus = []struct {
+	line string
+	want string
+}{
+	{"ADDSUBPD (BX), X11", "66 44 0f d0 1b"},
+	{"ADDSUBPD (BX), X2", "66 0f d0 13"},
+	{"ADDSUBPD (R11), X11", "66 45 0f d0 1b"},
+	{"ADDSUBPD (R11), X2", "66 41 0f d0 13"},
+	{"ADDSUBPD X11, X11", "66 45 0f d0 db"},
+	{"ADDSUBPD X11, X2", "66 41 0f d0 d3"},
+	{"ADDSUBPD X2, X11", "66 44 0f d0 da"},
+	{"ADDSUBPD X2, X2", "66 0f d0 d2"},
+	{"ADDSUBPS (BX), X11", "f2 44 0f d0 1b"},
+	{"ADDSUBPS (BX), X2", "f2 0f d0 13"},
+	{"ADDSUBPS (R11), X11", "f2 45 0f d0 1b"},
+	{"ADDSUBPS (R11), X2", "f2 41 0f d0 13"},
+	{"ADDSUBPS X11, X11", "f2 45 0f d0 db"},
+	{"ADDSUBPS X11, X2", "f2 41 0f d0 d3"},
+	{"ADDSUBPS X2, X11", "f2 44 0f d0 da"},
+	{"ADDSUBPS X2, X2", "f2 0f d0 d2"},
+	{"BLENDPD $7, (BX), X11", "66 44 0f 3a 0d 1b 07"},
+	{"BLENDPD $7, (BX), X2", "66 0f 3a 0d 13 07"},
+	{"BLENDPD $7, (R11), X11", "66 45 0f 3a 0d 1b 07"},
+	{"BLENDPD $7, (R11), X2", "66 41 0f 3a 0d 13 07"},
+	{"BLENDPD $7, X11, X11", "66 45 0f 3a 0d db 07"},
+	{"BLENDPD $7, X11, X2", "66 41 0f 3a 0d d3 07"},
+	{"BLENDPD $7, X2, X11", "66 44 0f 3a 0d da 07"},
+	{"BLENDPD $7, X2, X2", "66 0f 3a 0d d2 07"},
+	{"BLENDPS $7, (BX), X11", "66 44 0f 3a 0c 1b 07"},
+	{"BLENDPS $7, (BX), X2", "66 0f 3a 0c 13 07"},
+	{"BLENDPS $7, (R11), X11", "66 45 0f 3a 0c 1b 07"},
+	{"BLENDPS $7, (R11), X2", "66 41 0f 3a 0c 13 07"},
+	{"BLENDPS $7, X11, X11", "66 45 0f 3a 0c db 07"},
+	{"BLENDPS $7, X11, X2", "66 41 0f 3a 0c d3 07"},
+	{"BLENDPS $7, X2, X11", "66 44 0f 3a 0c da 07"},
+	{"BLENDPS $7, X2, X2", "66 0f 3a 0c d2 07"},
+	{"BLENDVPD X0, (BX), X11", "66 44 0f 38 15 1b"},
+	{"BLENDVPD X0, (BX), X2", "66 0f 38 15 13"},
+	{"BLENDVPD X0, (R11), X11", "66 45 0f 38 15 1b"},
+	{"BLENDVPD X0, (R11), X2", "66 41 0f 38 15 13"},
+	{"BLENDVPD X0, X11, X11", "66 45 0f 38 15 db"},
+	{"BLENDVPD X0, X11, X2", "66 41 0f 38 15 d3"},
+	{"BLENDVPD X0, X2, X11", "66 44 0f 38 15 da"},
+	{"BLENDVPD X0, X2, X2", "66 0f 38 15 d2"},
+	{"BLENDVPS X0, (BX), X11", "66 44 0f 38 14 1b"},
+	{"BLENDVPS X0, (BX), X2", "66 0f 38 14 13"},
+	{"BLENDVPS X0, (R11), X11", "66 45 0f 38 14 1b"},
+	{"BLENDVPS X0, (R11), X2", "66 41 0f 38 14 13"},
+	{"BLENDVPS X0, X11, X11", "66 45 0f 38 14 db"},
+	{"BLENDVPS X0, X11, X2", "66 41 0f 38 14 d3"},
+	{"BLENDVPS X0, X2, X11", "66 44 0f 38 14 da"},
+	{"BLENDVPS X0, X2, X2", "66 0f 38 14 d2"},
+	{"COMISS (BX), X11", "44 0f 2f 1b"},
+	{"COMISS (BX), X2", "0f 2f 13"},
+	{"COMISS (R11), X11", "45 0f 2f 1b"},
+	{"COMISS (R11), X2", "41 0f 2f 13"},
+	{"COMISS X11, X11", "45 0f 2f db"},
+	{"COMISS X11, X2", "41 0f 2f d3"},
+	{"COMISS X2, X11", "44 0f 2f da"},
+	{"COMISS X2, X2", "0f 2f d2"},
+	{"CVTPD2PL (BX), X11", "f2 44 0f e6 1b"},
+	{"CVTPD2PL (BX), X2", "f2 0f e6 13"},
+	{"CVTPD2PL (R11), X11", "f2 45 0f e6 1b"},
+	{"CVTPD2PL (R11), X2", "f2 41 0f e6 13"},
+	{"CVTPD2PL X11, X11", "f2 45 0f e6 db"},
+	{"CVTPD2PL X11, X2", "f2 41 0f e6 d3"},
+	{"CVTPD2PL X2, X11", "f2 44 0f e6 da"},
+	{"CVTPD2PL X2, X2", "f2 0f e6 d2"},
+	{"CVTPL2PD (BX), X11", "f3 44 0f e6 1b"},
+	{"CVTPL2PD (BX), X2", "f3 0f e6 13"},
+	{"CVTPL2PD (R11), X11", "f3 45 0f e6 1b"},
+	{"CVTPL2PD (R11), X2", "f3 41 0f e6 13"},
+	{"CVTPL2PD X11, X11", "f3 45 0f e6 db"},
+	{"CVTPL2PD X11, X2", "f3 41 0f e6 d3"},
+	{"CVTPL2PD X2, X11", "f3 44 0f e6 da"},
+	{"CVTPL2PD X2, X2", "f3 0f e6 d2"},
+	{"CVTPL2PS (BX), X11", "44 0f 5b 1b"},
+	{"CVTPL2PS (BX), X2", "0f 5b 13"},
+	{"CVTPL2PS (R11), X11", "45 0f 5b 1b"},
+	{"CVTPL2PS (R11), X2", "41 0f 5b 13"},
+	{"CVTPL2PS X11, X11", "45 0f 5b db"},
+	{"CVTPL2PS X11, X2", "41 0f 5b d3"},
+	{"CVTPL2PS X2, X11", "44 0f 5b da"},
+	{"CVTPL2PS X2, X2", "0f 5b d2"},
+	{"CVTPS2PL (BX), X11", "66 44 0f 5b 1b"},
+	{"CVTPS2PL (BX), X2", "66 0f 5b 13"},
+	{"CVTPS2PL (R11), X11", "66 45 0f 5b 1b"},
+	{"CVTPS2PL (R11), X2", "66 41 0f 5b 13"},
+	{"CVTPS2PL X11, X11", "66 45 0f 5b db"},
+	{"CVTPS2PL X11, X2", "66 41 0f 5b d3"},
+	{"CVTPS2PL X2, X11", "66 44 0f 5b da"},
+	{"CVTPS2PL X2, X2", "66 0f 5b d2"},
+	{"CVTSL2SS (BX), X11", "f3 44 0f 2a 1b"},
+	{"CVTSL2SS (BX), X2", "f3 0f 2a 13"},
+	{"CVTSL2SS (R11), X11", "f3 45 0f 2a 1b"},
+	{"CVTSL2SS (R11), X2", "f3 41 0f 2a 13"},
+	{"CVTSL2SS DX, X11", "f3 44 0f 2a da"},
+	{"CVTSL2SS DX, X2", "f3 0f 2a d2"},
+	{"CVTSL2SS R11, X11", "f3 45 0f 2a db"},
+	{"CVTSL2SS R11, X2", "f3 41 0f 2a d3"},
+	{"CVTSQ2SS (BX), X11", "f3 4c 0f 2a 1b"},
+	{"CVTSQ2SS (BX), X2", "f3 48 0f 2a 13"},
+	{"CVTSQ2SS (R11), X11", "f3 4d 0f 2a 1b"},
+	{"CVTSQ2SS (R11), X2", "f3 49 0f 2a 13"},
+	{"CVTSQ2SS DX, X11", "f3 4c 0f 2a da"},
+	{"CVTSQ2SS DX, X2", "f3 48 0f 2a d2"},
+	{"CVTSQ2SS R11, X11", "f3 4d 0f 2a db"},
+	{"CVTSQ2SS R11, X2", "f3 49 0f 2a d3"},
+	{"CVTTPD2PL (BX), X11", "66 44 0f e6 1b"},
+	{"CVTTPD2PL (BX), X2", "66 0f e6 13"},
+	{"CVTTPD2PL (R11), X11", "66 45 0f e6 1b"},
+	{"CVTTPD2PL (R11), X2", "66 41 0f e6 13"},
+	{"CVTTPD2PL X11, X11", "66 45 0f e6 db"},
+	{"CVTTPD2PL X11, X2", "66 41 0f e6 d3"},
+	{"CVTTPD2PL X2, X11", "66 44 0f e6 da"},
+	{"CVTTPD2PL X2, X2", "66 0f e6 d2"},
+	{"CVTTPS2PL (BX), X11", "f3 44 0f 5b 1b"},
+	{"CVTTPS2PL (BX), X2", "f3 0f 5b 13"},
+	{"CVTTPS2PL (R11), X11", "f3 45 0f 5b 1b"},
+	{"CVTTPS2PL (R11), X2", "f3 41 0f 5b 13"},
+	{"CVTTPS2PL X11, X11", "f3 45 0f 5b db"},
+	{"CVTTPS2PL X11, X2", "f3 41 0f 5b d3"},
+	{"CVTTPS2PL X2, X11", "f3 44 0f 5b da"},
+	{"CVTTPS2PL X2, X2", "f3 0f 5b d2"},
+	{"DPPD $7, (BX), X11", "66 44 0f 3a 41 1b 07"},
+	{"DPPD $7, (BX), X2", "66 0f 3a 41 13 07"},
+	{"DPPD $7, (R11), X11", "66 45 0f 3a 41 1b 07"},
+	{"DPPD $7, (R11), X2", "66 41 0f 3a 41 13 07"},
+	{"DPPD $7, X11, X11", "66 45 0f 3a 41 db 07"},
+	{"DPPD $7, X11, X2", "66 41 0f 3a 41 d3 07"},
+	{"DPPD $7, X2, X11", "66 44 0f 3a 41 da 07"},
+	{"DPPD $7, X2, X2", "66 0f 3a 41 d2 07"},
+	{"DPPS $7, (BX), X11", "66 44 0f 3a 40 1b 07"},
+	{"DPPS $7, (BX), X2", "66 0f 3a 40 13 07"},
+	{"DPPS $7, (R11), X11", "66 45 0f 3a 40 1b 07"},
+	{"DPPS $7, (R11), X2", "66 41 0f 3a 40 13 07"},
+	{"DPPS $7, X11, X11", "66 45 0f 3a 40 db 07"},
+	{"DPPS $7, X11, X2", "66 41 0f 3a 40 d3 07"},
+	{"DPPS $7, X2, X11", "66 44 0f 3a 40 da 07"},
+	{"DPPS $7, X2, X2", "66 0f 3a 40 d2 07"},
+	{"EMMS", "0f 77"},
+	{"EXTRACTPS $0, X11, R11", "66 45 0f 3a 17 db 00"},
+	{"EXTRACTPS $0, X2, (BX)", "66 0f 3a 17 13 00"},
+	{"EXTRACTPS $1, X11, (BX)", "66 44 0f 3a 17 1b 01"},
+	{"EXTRACTPS $1, X2, R11", "66 41 0f 3a 17 d3 01"},
+	{"EXTRACTPS $2, X11, DX", "66 44 0f 3a 17 da 02"},
+	{"EXTRACTPS $2, X2, (R11)", "66 41 0f 3a 17 13 02"},
+	{"EXTRACTPS $3, X11, (R11)", "66 45 0f 3a 17 1b 03"},
+	{"EXTRACTPS $3, X2, DX", "66 0f 3a 17 d2 03"},
+	{"HADDPD (BX), X11", "66 44 0f 7c 1b"},
+	{"HADDPD (BX), X2", "66 0f 7c 13"},
+	{"HADDPD (R11), X11", "66 45 0f 7c 1b"},
+	{"HADDPD (R11), X2", "66 41 0f 7c 13"},
+	{"HADDPD X11, X11", "66 45 0f 7c db"},
+	{"HADDPD X11, X2", "66 41 0f 7c d3"},
+	{"HADDPD X2, X11", "66 44 0f 7c da"},
+	{"HADDPD X2, X2", "66 0f 7c d2"},
+	{"HADDPS (BX), X11", "f2 44 0f 7c 1b"},
+	{"HADDPS (BX), X2", "f2 0f 7c 13"},
+	{"HADDPS (R11), X11", "f2 45 0f 7c 1b"},
+	{"HADDPS (R11), X2", "f2 41 0f 7c 13"},
+	{"HADDPS X11, X11", "f2 45 0f 7c db"},
+	{"HADDPS X11, X2", "f2 41 0f 7c d3"},
+	{"HADDPS X2, X11", "f2 44 0f 7c da"},
+	{"HADDPS X2, X2", "f2 0f 7c d2"},
+	{"HSUBPD (BX), X11", "66 44 0f 7d 1b"},
+	{"HSUBPD (BX), X2", "66 0f 7d 13"},
+	{"HSUBPD (R11), X11", "66 45 0f 7d 1b"},
+	{"HSUBPD (R11), X2", "66 41 0f 7d 13"},
+	{"HSUBPD X11, X11", "66 45 0f 7d db"},
+	{"HSUBPD X11, X2", "66 41 0f 7d d3"},
+	{"HSUBPD X2, X11", "66 44 0f 7d da"},
+	{"HSUBPD X2, X2", "66 0f 7d d2"},
+	{"HSUBPS (BX), X11", "f2 44 0f 7d 1b"},
+	{"HSUBPS (BX), X2", "f2 0f 7d 13"},
+	{"HSUBPS (R11), X11", "f2 45 0f 7d 1b"},
+	{"HSUBPS (R11), X2", "f2 41 0f 7d 13"},
+	{"HSUBPS X11, X11", "f2 45 0f 7d db"},
+	{"HSUBPS X11, X2", "f2 41 0f 7d d3"},
+	{"HSUBPS X2, X11", "f2 44 0f 7d da"},
+	{"HSUBPS X2, X2", "f2 0f 7d d2"},
+	{"INSERTPS $7, (BX), X11", "66 44 0f 3a 21 1b 07"},
+	{"INSERTPS $7, (BX), X2", "66 0f 3a 21 13 07"},
+	{"INSERTPS $7, (R11), X11", "66 45 0f 3a 21 1b 07"},
+	{"INSERTPS $7, (R11), X2", "66 41 0f 3a 21 13 07"},
+	{"INSERTPS $7, X11, X11", "66 45 0f 3a 21 db 07"},
+	{"INSERTPS $7, X11, X2", "66 41 0f 3a 21 d3 07"},
+	{"INSERTPS $7, X2, X11", "66 44 0f 3a 21 da 07"},
+	{"INSERTPS $7, X2, X2", "66 0f 3a 21 d2 07"},
+	{"LDDQU (BX), X11", "f2 44 0f f0 1b"},
+	{"LDDQU (BX), X2", "f2 0f f0 13"},
+	{"LDDQU (R11), X11", "f2 45 0f f0 1b"},
+	{"LDDQU (R11), X2", "f2 41 0f f0 13"},
+	{"MASKMOVOU X11, X11", "66 45 0f f7 db"},
+	{"MASKMOVOU X11, X2", "66 41 0f f7 d3"},
+	{"MASKMOVOU X2, X11", "66 44 0f f7 da"},
+	{"MASKMOVOU X2, X2", "66 0f f7 d2"},
+	{"MASKMOVQ M2, M2", "0f f7 d2"},
+	{"MASKMOVQ M2, M3", "0f f7 da"},
+	{"MASKMOVQ M3, M2", "0f f7 d3"},
+	{"MASKMOVQ M3, M3", "0f f7 db"},
+	{"MOVDDUP (BX), X11", "f2 44 0f 12 1b"},
+	{"MOVDDUP (BX), X2", "f2 0f 12 13"},
+	{"MOVDDUP (R11), X11", "f2 45 0f 12 1b"},
+	{"MOVDDUP (R11), X2", "f2 41 0f 12 13"},
+	{"MOVDDUP X11, X11", "f2 45 0f 12 db"},
+	{"MOVDDUP X11, X2", "f2 41 0f 12 d3"},
+	{"MOVDDUP X2, X11", "f2 44 0f 12 da"},
+	{"MOVDDUP X2, X2", "f2 0f 12 d2"},
+	{"MOVHLPS X11, X11", "45 0f 12 db"},
+	{"MOVHLPS X11, X2", "41 0f 12 d3"},
+	{"MOVHLPS X2, X11", "44 0f 12 da"},
+	{"MOVHLPS X2, X2", "0f 12 d2"},
+	{"MOVHPD (BX), X11", "66 44 0f 16 1b"},
+	{"MOVHPD (BX), X2", "66 0f 16 13"},
+	{"MOVHPD (R11), X11", "66 45 0f 16 1b"},
+	{"MOVHPD (R11), X2", "66 41 0f 16 13"},
+	{"MOVHPD X11, (BX)", "66 44 0f 17 1b"},
+	{"MOVHPD X11, (R11)", "66 45 0f 17 1b"},
+	{"MOVHPD X2, (BX)", "66 0f 17 13"},
+	{"MOVHPD X2, (R11)", "66 41 0f 17 13"},
+	{"MOVHPS (BX), X11", "44 0f 16 1b"},
+	{"MOVHPS (BX), X2", "0f 16 13"},
+	{"MOVHPS (R11), X11", "45 0f 16 1b"},
+	{"MOVHPS (R11), X2", "41 0f 16 13"},
+	{"MOVHPS X11, (BX)", "44 0f 17 1b"},
+	{"MOVHPS X11, (R11)", "45 0f 17 1b"},
+	{"MOVHPS X2, (BX)", "0f 17 13"},
+	{"MOVHPS X2, (R11)", "41 0f 17 13"},
+	{"MOVLHPS X11, X11", "45 0f 16 db"},
+	{"MOVLHPS X11, X2", "41 0f 16 d3"},
+	{"MOVLHPS X2, X11", "44 0f 16 da"},
+	{"MOVLHPS X2, X2", "0f 16 d2"},
+	{"MOVLPD (BX), X11", "66 44 0f 12 1b"},
+	{"MOVLPD (BX), X2", "66 0f 12 13"},
+	{"MOVLPD (R11), X11", "66 45 0f 12 1b"},
+	{"MOVLPD (R11), X2", "66 41 0f 12 13"},
+	{"MOVLPD X11, (BX)", "66 44 0f 13 1b"},
+	{"MOVLPD X11, (R11)", "66 45 0f 13 1b"},
+	{"MOVLPD X2, (BX)", "66 0f 13 13"},
+	{"MOVLPD X2, (R11)", "66 41 0f 13 13"},
+	{"MOVLPS (BX), X11", "44 0f 12 1b"},
+	{"MOVLPS (BX), X2", "0f 12 13"},
+	{"MOVLPS (R11), X11", "45 0f 12 1b"},
+	{"MOVLPS (R11), X2", "41 0f 12 13"},
+	{"MOVLPS X11, (BX)", "44 0f 13 1b"},
+	{"MOVLPS X11, (R11)", "45 0f 13 1b"},
+	{"MOVLPS X2, (BX)", "0f 13 13"},
+	{"MOVLPS X2, (R11)", "41 0f 13 13"},
+	{"MOVMSKPD X11, DX", "66 41 0f 50 d3"},
+	{"MOVMSKPD X11, R11", "66 45 0f 50 db"},
+	{"MOVMSKPD X2, DX", "66 0f 50 d2"},
+	{"MOVMSKPD X2, R11", "66 44 0f 50 da"},
+	{"MOVMSKPS X11, DX", "41 0f 50 d3"},
+	{"MOVMSKPS X11, R11", "45 0f 50 db"},
+	{"MOVMSKPS X2, DX", "0f 50 d2"},
+	{"MOVMSKPS X2, R11", "44 0f 50 da"},
+	{"MOVNTDQA (BX), X11", "66 44 0f 38 2a 1b"},
+	{"MOVNTDQA (BX), X2", "66 0f 38 2a 13"},
+	{"MOVNTDQA (R11), X11", "66 45 0f 38 2a 1b"},
+	{"MOVNTDQA (R11), X2", "66 41 0f 38 2a 13"},
+	{"MOVNTIL DX, (BX)", "0f c3 13"},
+	{"MOVNTIL DX, (R11)", "41 0f c3 13"},
+	{"MOVNTIL R11, (BX)", "44 0f c3 1b"},
+	{"MOVNTIL R11, (R11)", "45 0f c3 1b"},
+	{"MOVNTIQ DX, (BX)", "48 0f c3 13"},
+	{"MOVNTIQ DX, (R11)", "49 0f c3 13"},
+	{"MOVNTIQ R11, (BX)", "4c 0f c3 1b"},
+	{"MOVNTIQ R11, (R11)", "4d 0f c3 1b"},
+	{"MOVNTO X11, (BX)", "66 44 0f e7 1b"},
+	{"MOVNTO X11, (R11)", "66 45 0f e7 1b"},
+	{"MOVNTO X2, (BX)", "66 0f e7 13"},
+	{"MOVNTO X2, (R11)", "66 41 0f e7 13"},
+	{"MOVNTPD X11, (BX)", "66 44 0f 2b 1b"},
+	{"MOVNTPD X11, (R11)", "66 45 0f 2b 1b"},
+	{"MOVNTPD X2, (BX)", "66 0f 2b 13"},
+	{"MOVNTPD X2, (R11)", "66 41 0f 2b 13"},
+	{"MOVNTPS X11, (BX)", "44 0f 2b 1b"},
+	{"MOVNTPS X11, (R11)", "45 0f 2b 1b"},
+	{"MOVNTPS X2, (BX)", "0f 2b 13"},
+	{"MOVNTPS X2, (R11)", "41 0f 2b 13"},
+	{"MOVNTQ M2, (BX)", "0f e7 13"},
+	{"MOVNTQ M2, (R11)", "41 0f e7 13"},
+	{"MOVNTQ M3, (BX)", "0f e7 1b"},
+	{"MOVNTQ M3, (R11)", "41 0f e7 1b"},
+	{"MOVQ $-1070935975390360081, DX", "48 ba ef cd ab 89 67 45 23 f1"},
+	{"MOVQ $-1070935975390360081, R11", "49 bb ef cd ab 89 67 45 23 f1"},
+	{"MOVQ $-249346713, (BX)", "48 c7 03 67 45 23 f1"},
+	{"MOVQ $-249346713, (R11)", "49 c7 03 67 45 23 f1"},
+	{"MOVQ $-249346713, DX", "48 c7 c2 67 45 23 f1"},
+	{"MOVQ $-249346713, R11", "49 c7 c3 67 45 23 f1"},
+	{"MOVQ $2147483648, DX", "ba 00 00 00 80"},
+	{"MOVQ $2147483648, R11", "41 bb 00 00 00 80"},
+	{"MOVQ $305419896, DX", "ba 78 56 34 12"},
+	{"MOVQ $305419896, R11", "41 bb 78 56 34 12"},
+	{"MOVQ $4294967295, DX", "ba ff ff ff ff"},
+	{"MOVQ $4294967295, R11", "41 bb ff ff ff ff"},
+	{"MOVQ (BX), DX", "48 8b 13"},
+	{"MOVQ (BX), M2", "0f 6f 13"},
+	{"MOVQ (BX), M3", "0f 6f 1b"},
+	{"MOVQ (BX), R11", "4c 8b 1b"},
+	{"MOVQ (BX), X11", "f3 44 0f 7e 1b"},
+	{"MOVQ (BX), X2", "f3 0f 7e 13"},
+	{"MOVQ (R11), DX", "49 8b 13"},
+	{"MOVQ (R11), M2", "41 0f 6f 13"},
+	{"MOVQ (R11), M3", "41 0f 6f 1b"},
+	{"MOVQ (R11), R11", "4d 8b 1b"},
+	{"MOVQ (R11), X11", "f3 45 0f 7e 1b"},
+	{"MOVQ (R11), X2", "f3 41 0f 7e 13"},
+	{"MOVQ CR2, DX", "0f 20 d2"},
+	{"MOVQ CR2, R11", "41 0f 20 d3"},
+	{"MOVQ CR3, DX", "0f 20 da"},
+	{"MOVQ CR3, R11", "41 0f 20 db"},
+	{"MOVQ DR2, DX", "0f 21 d2"},
+	{"MOVQ DR2, R11", "41 0f 21 d3"},
+	{"MOVQ DR3, DX", "0f 21 da"},
+	{"MOVQ DR3, R11", "41 0f 21 db"},
+	{"MOVQ DX, (BX)", "48 89 13"},
+	{"MOVQ DX, (R11)", "49 89 13"},
+	{"MOVQ DX, CR2", "0f 22 d2"},
+	{"MOVQ DX, CR3", "0f 22 da"},
+	{"MOVQ DX, DR2", "0f 23 d2"},
+	{"MOVQ DX, DR3", "0f 23 da"},
+	{"MOVQ DX, DX", "48 89 d2"},
+	{"MOVQ DX, M2", "48 0f 6e d2"},
+	{"MOVQ DX, M3", "48 0f 6e da"},
+	{"MOVQ DX, R11", "49 89 d3"},
+	{"MOVQ DX, X11", "66 4c 0f 6e da"},
+	{"MOVQ DX, X2", "66 48 0f 6e d2"},
+	{"MOVQ M2, (BX)", "0f 7f 13"},
+	{"MOVQ M2, (R11)", "41 0f 7f 13"},
+	{"MOVQ M2, DX", "48 0f 7e d2"},
+	{"MOVQ M2, R11", "49 0f 7e d3"},
+	{"MOVQ M3, (BX)", "0f 7f 1b"},
+	{"MOVQ M3, (R11)", "41 0f 7f 1b"},
+	{"MOVQ M3, DX", "48 0f 7e da"},
+	{"MOVQ M3, R11", "49 0f 7e db"},
+	{"MOVQ R11, (BX)", "4c 89 1b"},
+	{"MOVQ R11, (R11)", "4d 89 1b"},
+	{"MOVQ R11, CR2", "41 0f 22 d3"},
+	{"MOVQ R11, CR3", "41 0f 22 db"},
+	{"MOVQ R11, DR2", "41 0f 23 d3"},
+	{"MOVQ R11, DR3", "41 0f 23 db"},
+	{"MOVQ R11, DX", "4c 89 da"},
+	{"MOVQ R11, M2", "49 0f 6e d3"},
+	{"MOVQ R11, M3", "49 0f 6e db"},
+	{"MOVQ R11, R11", "4d 89 db"},
+	{"MOVQ R11, X11", "66 4d 0f 6e db"},
+	{"MOVQ R11, X2", "66 49 0f 6e d3"},
+	{"MOVQ X11, (BX)", "66 44 0f d6 1b"},
+	{"MOVQ X11, (R11)", "66 45 0f d6 1b"},
+	{"MOVQ X11, DX", "66 4c 0f 7e da"},
+	{"MOVQ X11, M2", "f2 41 0f d6 d3"},
+	{"MOVQ X11, M3", "f2 41 0f d6 db"},
+	{"MOVQ X11, R11", "66 4d 0f 7e db"},
+	{"MOVQ X11, X11", "f3 45 0f 7e db"},
+	{"MOVQ X11, X2", "f3 41 0f 7e d3"},
+	{"MOVQ X2, (BX)", "66 0f d6 13"},
+	{"MOVQ X2, (R11)", "66 41 0f d6 13"},
+	{"MOVQ X2, DX", "66 48 0f 7e d2"},
+	{"MOVQ X2, M2", "f2 0f d6 d2"},
+	{"MOVQ X2, M3", "f2 0f d6 da"},
+	{"MOVQ X2, R11", "66 49 0f 7e d3"},
+	{"MOVQ X2, X11", "f3 44 0f 7e da"},
+	{"MOVQ X2, X2", "f3 0f 7e d2"},
+	{"MOVQOZX M2, X11", "f3 44 0f d6 da"},
+	{"MOVQOZX M2, X2", "f3 0f d6 d2"},
+	{"MOVQOZX M3, X11", "f3 44 0f d6 db"},
+	{"MOVQOZX M3, X2", "f3 0f d6 d3"},
+	{"MOVSHDUP (BX), X11", "f3 44 0f 16 1b"},
+	{"MOVSHDUP (BX), X2", "f3 0f 16 13"},
+	{"MOVSHDUP (R11), X11", "f3 45 0f 16 1b"},
+	{"MOVSHDUP (R11), X2", "f3 41 0f 16 13"},
+	{"MOVSHDUP X11, X11", "f3 45 0f 16 db"},
+	{"MOVSHDUP X11, X2", "f3 41 0f 16 d3"},
+	{"MOVSHDUP X2, X11", "f3 44 0f 16 da"},
+	{"MOVSHDUP X2, X2", "f3 0f 16 d2"},
+	{"MOVSLDUP (BX), X11", "f3 44 0f 12 1b"},
+	{"MOVSLDUP (BX), X2", "f3 0f 12 13"},
+	{"MOVSLDUP (R11), X11", "f3 45 0f 12 1b"},
+	{"MOVSLDUP (R11), X2", "f3 41 0f 12 13"},
+	{"MOVSLDUP X11, X11", "f3 45 0f 12 db"},
+	{"MOVSLDUP X11, X2", "f3 41 0f 12 d3"},
+	{"MOVSLDUP X2, X11", "f3 44 0f 12 da"},
+	{"MOVSLDUP X2, X2", "f3 0f 12 d2"},
+	{"MOVSWW (BX), DX", "66 0f bf 13"},
+	{"MOVSWW (BX), R11", "66 44 0f bf 1b"},
+	{"MOVSWW (R11), DX", "66 41 0f bf 13"},
+	{"MOVSWW (R11), R11", "66 45 0f bf 1b"},
+	{"MOVSWW DX, DX", "66 0f bf d2"},
+	{"MOVSWW DX, R11", "66 44 0f bf da"},
+	{"MOVSWW R11, DX", "66 41 0f bf d3"},
+	{"MOVSWW R11, R11", "66 45 0f bf db"},
+	{"MOVZWW (BX), DX", "66 0f b7 13"},
+	{"MOVZWW (BX), R11", "66 44 0f b7 1b"},
+	{"MOVZWW (R11), DX", "66 41 0f b7 13"},
+	{"MOVZWW (R11), R11", "66 45 0f b7 1b"},
+	{"MOVZWW DX, DX", "66 0f b7 d2"},
+	{"MOVZWW DX, R11", "66 44 0f b7 da"},
+	{"MOVZWW R11, DX", "66 41 0f b7 d3"},
+	{"MOVZWW R11, R11", "66 45 0f b7 db"},
+	{"MPSADBW $7, (BX), X11", "66 44 0f 3a 42 1b 07"},
+	{"MPSADBW $7, (BX), X2", "66 0f 3a 42 13 07"},
+	{"MPSADBW $7, (R11), X11", "66 45 0f 3a 42 1b 07"},
+	{"MPSADBW $7, (R11), X2", "66 41 0f 3a 42 13 07"},
+	{"MPSADBW $7, X11, X11", "66 45 0f 3a 42 db 07"},
+	{"MPSADBW $7, X11, X2", "66 41 0f 3a 42 d3 07"},
+	{"MPSADBW $7, X2, X11", "66 44 0f 3a 42 da 07"},
+	{"MPSADBW $7, X2, X2", "66 0f 3a 42 d2 07"},
+	{"PABSB (BX), X11", "66 44 0f 38 1c 1b"},
+	{"PABSB (BX), X2", "66 0f 38 1c 13"},
+	{"PABSB (R11), X11", "66 45 0f 38 1c 1b"},
+	{"PABSB (R11), X2", "66 41 0f 38 1c 13"},
+	{"PABSB X11, X11", "66 45 0f 38 1c db"},
+	{"PABSB X11, X2", "66 41 0f 38 1c d3"},
+	{"PABSB X2, X11", "66 44 0f 38 1c da"},
+	{"PABSB X2, X2", "66 0f 38 1c d2"},
+	{"PABSD (BX), X11", "66 44 0f 38 1e 1b"},
+	{"PABSD (BX), X2", "66 0f 38 1e 13"},
+	{"PABSD (R11), X11", "66 45 0f 38 1e 1b"},
+	{"PABSD (R11), X2", "66 41 0f 38 1e 13"},
+	{"PABSD X11, X11", "66 45 0f 38 1e db"},
+	{"PABSD X11, X2", "66 41 0f 38 1e d3"},
+	{"PABSD X2, X11", "66 44 0f 38 1e da"},
+	{"PABSD X2, X2", "66 0f 38 1e d2"},
+	{"PABSW (BX), X11", "66 44 0f 38 1d 1b"},
+	{"PABSW (BX), X2", "66 0f 38 1d 13"},
+	{"PABSW (R11), X11", "66 45 0f 38 1d 1b"},
+	{"PABSW (R11), X2", "66 41 0f 38 1d 13"},
+	{"PABSW X11, X11", "66 45 0f 38 1d db"},
+	{"PABSW X11, X2", "66 41 0f 38 1d d3"},
+	{"PABSW X2, X11", "66 44 0f 38 1d da"},
+	{"PABSW X2, X2", "66 0f 38 1d d2"},
+	{"PACKSSLW (BX), M2", "0f 6b 13"},
+	{"PACKSSLW (BX), M3", "0f 6b 1b"},
+	{"PACKSSLW (BX), X11", "66 44 0f 6b 1b"},
+	{"PACKSSLW (BX), X2", "66 0f 6b 13"},
+	{"PACKSSLW (R11), M2", "41 0f 6b 13"},
+	{"PACKSSLW (R11), M3", "41 0f 6b 1b"},
+	{"PACKSSLW (R11), X11", "66 45 0f 6b 1b"},
+	{"PACKSSLW (R11), X2", "66 41 0f 6b 13"},
+	{"PACKSSLW M2, M2", "0f 6b d2"},
+	{"PACKSSLW M2, M3", "0f 6b da"},
+	{"PACKSSLW M3, M2", "0f 6b d3"},
+	{"PACKSSLW M3, M3", "0f 6b db"},
+	{"PACKSSLW X11, X11", "66 45 0f 6b db"},
+	{"PACKSSLW X11, X2", "66 41 0f 6b d3"},
+	{"PACKSSLW X2, X11", "66 44 0f 6b da"},
+	{"PACKSSLW X2, X2", "66 0f 6b d2"},
+	{"PACKSSWB (BX), M2", "0f 63 13"},
+	{"PACKSSWB (BX), M3", "0f 63 1b"},
+	{"PACKSSWB (BX), X11", "66 44 0f 63 1b"},
+	{"PACKSSWB (BX), X2", "66 0f 63 13"},
+	{"PACKSSWB (R11), M2", "41 0f 63 13"},
+	{"PACKSSWB (R11), M3", "41 0f 63 1b"},
+	{"PACKSSWB (R11), X11", "66 45 0f 63 1b"},
+	{"PACKSSWB (R11), X2", "66 41 0f 63 13"},
+	{"PACKSSWB M2, M2", "0f 63 d2"},
+	{"PACKSSWB M2, M3", "0f 63 da"},
+	{"PACKSSWB M3, M2", "0f 63 d3"},
+	{"PACKSSWB M3, M3", "0f 63 db"},
+	{"PACKSSWB X11, X11", "66 45 0f 63 db"},
+	{"PACKSSWB X11, X2", "66 41 0f 63 d3"},
+	{"PACKSSWB X2, X11", "66 44 0f 63 da"},
+	{"PACKSSWB X2, X2", "66 0f 63 d2"},
+	{"PACKUSDW (BX), X11", "66 44 0f 38 2b 1b"},
+	{"PACKUSDW (BX), X2", "66 0f 38 2b 13"},
+	{"PACKUSDW (R11), X11", "66 45 0f 38 2b 1b"},
+	{"PACKUSDW (R11), X2", "66 41 0f 38 2b 13"},
+	{"PACKUSDW X11, X11", "66 45 0f 38 2b db"},
+	{"PACKUSDW X11, X2", "66 41 0f 38 2b d3"},
+	{"PACKUSDW X2, X11", "66 44 0f 38 2b da"},
+	{"PACKUSDW X2, X2", "66 0f 38 2b d2"},
+	{"PACKUSWB (BX), M2", "0f 67 13"},
+	{"PACKUSWB (BX), M3", "0f 67 1b"},
+	{"PACKUSWB (BX), X11", "66 44 0f 67 1b"},
+	{"PACKUSWB (BX), X2", "66 0f 67 13"},
+	{"PACKUSWB (R11), M2", "41 0f 67 13"},
+	{"PACKUSWB (R11), M3", "41 0f 67 1b"},
+	{"PACKUSWB (R11), X11", "66 45 0f 67 1b"},
+	{"PACKUSWB (R11), X2", "66 41 0f 67 13"},
+	{"PACKUSWB M2, M2", "0f 67 d2"},
+	{"PACKUSWB M2, M3", "0f 67 da"},
+	{"PACKUSWB M3, M2", "0f 67 d3"},
+	{"PACKUSWB M3, M3", "0f 67 db"},
+	{"PACKUSWB X11, X11", "66 45 0f 67 db"},
+	{"PACKUSWB X11, X2", "66 41 0f 67 d3"},
+	{"PACKUSWB X2, X11", "66 44 0f 67 da"},
+	{"PACKUSWB X2, X2", "66 0f 67 d2"},
+	{"PADDSB (BX), M2", "0f ec 13"},
+	{"PADDSB (BX), M3", "0f ec 1b"},
+	{"PADDSB (BX), X11", "66 44 0f ec 1b"},
+	{"PADDSB (BX), X2", "66 0f ec 13"},
+	{"PADDSB (R11), M2", "41 0f ec 13"},
+	{"PADDSB (R11), M3", "41 0f ec 1b"},
+	{"PADDSB (R11), X11", "66 45 0f ec 1b"},
+	{"PADDSB (R11), X2", "66 41 0f ec 13"},
+	{"PADDSB M2, M2", "0f ec d2"},
+	{"PADDSB M2, M3", "0f ec da"},
+	{"PADDSB M3, M2", "0f ec d3"},
+	{"PADDSB M3, M3", "0f ec db"},
+	{"PADDSB X11, X11", "66 45 0f ec db"},
+	{"PADDSB X11, X2", "66 41 0f ec d3"},
+	{"PADDSB X2, X11", "66 44 0f ec da"},
+	{"PADDSB X2, X2", "66 0f ec d2"},
+	{"PADDSW (BX), M2", "0f ed 13"},
+	{"PADDSW (BX), M3", "0f ed 1b"},
+	{"PADDSW (BX), X11", "66 44 0f ed 1b"},
+	{"PADDSW (BX), X2", "66 0f ed 13"},
+	{"PADDSW (R11), M2", "41 0f ed 13"},
+	{"PADDSW (R11), M3", "41 0f ed 1b"},
+	{"PADDSW (R11), X11", "66 45 0f ed 1b"},
+	{"PADDSW (R11), X2", "66 41 0f ed 13"},
+	{"PADDSW M2, M2", "0f ed d2"},
+	{"PADDSW M2, M3", "0f ed da"},
+	{"PADDSW M3, M2", "0f ed d3"},
+	{"PADDSW M3, M3", "0f ed db"},
+	{"PADDSW X11, X11", "66 45 0f ed db"},
+	{"PADDSW X11, X2", "66 41 0f ed d3"},
+	{"PADDSW X2, X11", "66 44 0f ed da"},
+	{"PADDSW X2, X2", "66 0f ed d2"},
+	{"PADDUSB (BX), M2", "0f dc 13"},
+	{"PADDUSB (BX), M3", "0f dc 1b"},
+	{"PADDUSB (BX), X11", "66 44 0f dc 1b"},
+	{"PADDUSB (BX), X2", "66 0f dc 13"},
+	{"PADDUSB (R11), M2", "41 0f dc 13"},
+	{"PADDUSB (R11), M3", "41 0f dc 1b"},
+	{"PADDUSB (R11), X11", "66 45 0f dc 1b"},
+	{"PADDUSB (R11), X2", "66 41 0f dc 13"},
+	{"PADDUSB M2, M2", "0f dc d2"},
+	{"PADDUSB M2, M3", "0f dc da"},
+	{"PADDUSB M3, M2", "0f dc d3"},
+	{"PADDUSB M3, M3", "0f dc db"},
+	{"PADDUSB X11, X11", "66 45 0f dc db"},
+	{"PADDUSB X11, X2", "66 41 0f dc d3"},
+	{"PADDUSB X2, X11", "66 44 0f dc da"},
+	{"PADDUSB X2, X2", "66 0f dc d2"},
+	{"PADDUSW (BX), M2", "0f dd 13"},
+	{"PADDUSW (BX), M3", "0f dd 1b"},
+	{"PADDUSW (BX), X11", "66 44 0f dd 1b"},
+	{"PADDUSW (BX), X2", "66 0f dd 13"},
+	{"PADDUSW (R11), M2", "41 0f dd 13"},
+	{"PADDUSW (R11), M3", "41 0f dd 1b"},
+	{"PADDUSW (R11), X11", "66 45 0f dd 1b"},
+	{"PADDUSW (R11), X2", "66 41 0f dd 13"},
+	{"PADDUSW M2, M2", "0f dd d2"},
+	{"PADDUSW M2, M3", "0f dd da"},
+	{"PADDUSW M3, M2", "0f dd d3"},
+	{"PADDUSW M3, M3", "0f dd db"},
+	{"PADDUSW X11, X11", "66 45 0f dd db"},
+	{"PADDUSW X11, X2", "66 41 0f dd d3"},
+	{"PADDUSW X2, X11", "66 44 0f dd da"},
+	{"PADDUSW X2, X2", "66 0f dd d2"},
+	{"PAVGB (BX), M2", "0f e0 13"},
+	{"PAVGB (BX), M3", "0f e0 1b"},
+	{"PAVGB (BX), X11", "66 44 0f e0 1b"},
+	{"PAVGB (BX), X2", "66 0f e0 13"},
+	{"PAVGB (R11), M2", "41 0f e0 13"},
+	{"PAVGB (R11), M3", "41 0f e0 1b"},
+	{"PAVGB (R11), X11", "66 45 0f e0 1b"},
+	{"PAVGB (R11), X2", "66 41 0f e0 13"},
+	{"PAVGB M2, M2", "0f e0 d2"},
+	{"PAVGB M2, M3", "0f e0 da"},
+	{"PAVGB M3, M2", "0f e0 d3"},
+	{"PAVGB M3, M3", "0f e0 db"},
+	{"PAVGB X11, X11", "66 45 0f e0 db"},
+	{"PAVGB X11, X2", "66 41 0f e0 d3"},
+	{"PAVGB X2, X11", "66 44 0f e0 da"},
+	{"PAVGB X2, X2", "66 0f e0 d2"},
+	{"PAVGW (BX), M2", "0f e3 13"},
+	{"PAVGW (BX), M3", "0f e3 1b"},
+	{"PAVGW (BX), X11", "66 44 0f e3 1b"},
+	{"PAVGW (BX), X2", "66 0f e3 13"},
+	{"PAVGW (R11), M2", "41 0f e3 13"},
+	{"PAVGW (R11), M3", "41 0f e3 1b"},
+	{"PAVGW (R11), X11", "66 45 0f e3 1b"},
+	{"PAVGW (R11), X2", "66 41 0f e3 13"},
+	{"PAVGW M2, M2", "0f e3 d2"},
+	{"PAVGW M2, M3", "0f e3 da"},
+	{"PAVGW M3, M2", "0f e3 d3"},
+	{"PAVGW M3, M3", "0f e3 db"},
+	{"PAVGW X11, X11", "66 45 0f e3 db"},
+	{"PAVGW X11, X2", "66 41 0f e3 d3"},
+	{"PAVGW X2, X11", "66 44 0f e3 da"},
+	{"PAVGW X2, X2", "66 0f e3 d2"},
+	{"PBLENDVB X0, (BX), X11", "66 44 0f 38 10 1b"},
+	{"PBLENDVB X0, (BX), X2", "66 0f 38 10 13"},
+	{"PBLENDVB X0, (R11), X11", "66 45 0f 38 10 1b"},
+	{"PBLENDVB X0, (R11), X2", "66 41 0f 38 10 13"},
+	{"PBLENDVB X0, X11, X11", "66 45 0f 38 10 db"},
+	{"PBLENDVB X0, X11, X2", "66 41 0f 38 10 d3"},
+	{"PBLENDVB X0, X2, X11", "66 44 0f 38 10 da"},
+	{"PBLENDVB X0, X2, X2", "66 0f 38 10 d2"},
+	{"PCMPEQQ (BX), X11", "66 44 0f 38 29 1b"},
+	{"PCMPEQQ (BX), X2", "66 0f 38 29 13"},
+	{"PCMPEQQ (R11), X11", "66 45 0f 38 29 1b"},
+	{"PCMPEQQ (R11), X2", "66 41 0f 38 29 13"},
+	{"PCMPEQQ X11, X11", "66 45 0f 38 29 db"},
+	{"PCMPEQQ X11, X2", "66 41 0f 38 29 d3"},
+	{"PCMPEQQ X2, X11", "66 44 0f 38 29 da"},
+	{"PCMPEQQ X2, X2", "66 0f 38 29 d2"},
+	{"PCMPESTRM $7, (BX), X11", "66 44 0f 3a 60 1b 07"},
+	{"PCMPESTRM $7, (BX), X2", "66 0f 3a 60 13 07"},
+	{"PCMPESTRM $7, (R11), X11", "66 45 0f 3a 60 1b 07"},
+	{"PCMPESTRM $7, (R11), X2", "66 41 0f 3a 60 13 07"},
+	{"PCMPESTRM $7, X11, X11", "66 45 0f 3a 60 db 07"},
+	{"PCMPESTRM $7, X11, X2", "66 41 0f 3a 60 d3 07"},
+	{"PCMPESTRM $7, X2, X11", "66 44 0f 3a 60 da 07"},
+	{"PCMPESTRM $7, X2, X2", "66 0f 3a 60 d2 07"},
+	{"PCMPGTL (BX), M2", "0f 66 13"},
+	{"PCMPGTL (BX), M3", "0f 66 1b"},
+	{"PCMPGTL (BX), X11", "66 44 0f 66 1b"},
+	{"PCMPGTL (BX), X2", "66 0f 66 13"},
+	{"PCMPGTL (R11), M2", "41 0f 66 13"},
+	{"PCMPGTL (R11), M3", "41 0f 66 1b"},
+	{"PCMPGTL (R11), X11", "66 45 0f 66 1b"},
+	{"PCMPGTL (R11), X2", "66 41 0f 66 13"},
+	{"PCMPGTL M2, M2", "0f 66 d2"},
+	{"PCMPGTL M2, M3", "0f 66 da"},
+	{"PCMPGTL M3, M2", "0f 66 d3"},
+	{"PCMPGTL M3, M3", "0f 66 db"},
+	{"PCMPGTL X11, X11", "66 45 0f 66 db"},
+	{"PCMPGTL X11, X2", "66 41 0f 66 d3"},
+	{"PCMPGTL X2, X11", "66 44 0f 66 da"},
+	{"PCMPGTL X2, X2", "66 0f 66 d2"},
+	{"PCMPGTQ (BX), X11", "66 44 0f 38 37 1b"},
+	{"PCMPGTQ (BX), X2", "66 0f 38 37 13"},
+	{"PCMPGTQ (R11), X11", "66 45 0f 38 37 1b"},
+	{"PCMPGTQ (R11), X2", "66 41 0f 38 37 13"},
+	{"PCMPGTQ X11, X11", "66 45 0f 38 37 db"},
+	{"PCMPGTQ X11, X2", "66 41 0f 38 37 d3"},
+	{"PCMPGTQ X2, X11", "66 44 0f 38 37 da"},
+	{"PCMPGTQ X2, X2", "66 0f 38 37 d2"},
+	{"PCMPISTRI $7, (BX), X11", "66 44 0f 3a 63 1b 07"},
+	{"PCMPISTRI $7, (BX), X2", "66 0f 3a 63 13 07"},
+	{"PCMPISTRI $7, (R11), X11", "66 45 0f 3a 63 1b 07"},
+	{"PCMPISTRI $7, (R11), X2", "66 41 0f 3a 63 13 07"},
+	{"PCMPISTRI $7, X11, X11", "66 45 0f 3a 63 db 07"},
+	{"PCMPISTRI $7, X11, X2", "66 41 0f 3a 63 d3 07"},
+	{"PCMPISTRI $7, X2, X11", "66 44 0f 3a 63 da 07"},
+	{"PCMPISTRI $7, X2, X2", "66 0f 3a 63 d2 07"},
+	{"PCMPISTRM $7, (BX), X11", "66 44 0f 3a 62 1b 07"},
+	{"PCMPISTRM $7, (BX), X2", "66 0f 3a 62 13 07"},
+	{"PCMPISTRM $7, (R11), X11", "66 45 0f 3a 62 1b 07"},
+	{"PCMPISTRM $7, (R11), X2", "66 41 0f 3a 62 13 07"},
+	{"PCMPISTRM $7, X11, X11", "66 45 0f 3a 62 db 07"},
+	{"PCMPISTRM $7, X11, X2", "66 41 0f 3a 62 d3 07"},
+	{"PCMPISTRM $7, X2, X11", "66 44 0f 3a 62 da 07"},
+	{"PCMPISTRM $7, X2, X2", "66 0f 3a 62 d2 07"},
+	{"PHADDD (BX), M2", "0f 38 02 13"},
+	{"PHADDD (BX), M3", "0f 38 02 1b"},
+	{"PHADDD (BX), X11", "66 44 0f 38 02 1b"},
+	{"PHADDD (BX), X2", "66 0f 38 02 13"},
+	{"PHADDD (R11), M2", "41 0f 38 02 13"},
+	{"PHADDD (R11), M3", "41 0f 38 02 1b"},
+	{"PHADDD (R11), X11", "66 45 0f 38 02 1b"},
+	{"PHADDD (R11), X2", "66 41 0f 38 02 13"},
+	{"PHADDD M2, M2", "0f 38 02 d2"},
+	{"PHADDD M2, M3", "0f 38 02 da"},
+	{"PHADDD M3, M2", "0f 38 02 d3"},
+	{"PHADDD M3, M3", "0f 38 02 db"},
+	{"PHADDD X11, X11", "66 45 0f 38 02 db"},
+	{"PHADDD X11, X2", "66 41 0f 38 02 d3"},
+	{"PHADDD X2, X11", "66 44 0f 38 02 da"},
+	{"PHADDD X2, X2", "66 0f 38 02 d2"},
+	{"PHADDSW (BX), X11", "66 44 0f 38 03 1b"},
+	{"PHADDSW (BX), X2", "66 0f 38 03 13"},
+	{"PHADDSW (R11), X11", "66 45 0f 38 03 1b"},
+	{"PHADDSW (R11), X2", "66 41 0f 38 03 13"},
+	{"PHADDSW X11, X11", "66 45 0f 38 03 db"},
+	{"PHADDSW X11, X2", "66 41 0f 38 03 d3"},
+	{"PHADDSW X2, X11", "66 44 0f 38 03 da"},
+	{"PHADDSW X2, X2", "66 0f 38 03 d2"},
+	{"PHADDW (BX), X11", "66 44 0f 38 01 1b"},
+	{"PHADDW (BX), X2", "66 0f 38 01 13"},
+	{"PHADDW (R11), X11", "66 45 0f 38 01 1b"},
+	{"PHADDW (R11), X2", "66 41 0f 38 01 13"},
+	{"PHADDW X11, X11", "66 45 0f 38 01 db"},
+	{"PHADDW X11, X2", "66 41 0f 38 01 d3"},
+	{"PHADDW X2, X11", "66 44 0f 38 01 da"},
+	{"PHADDW X2, X2", "66 0f 38 01 d2"},
+	{"PHMINPOSUW (BX), X11", "66 44 0f 38 41 1b"},
+	{"PHMINPOSUW (BX), X2", "66 0f 38 41 13"},
+	{"PHMINPOSUW (R11), X11", "66 45 0f 38 41 1b"},
+	{"PHMINPOSUW (R11), X2", "66 41 0f 38 41 13"},
+	{"PHMINPOSUW X11, X11", "66 45 0f 38 41 db"},
+	{"PHMINPOSUW X11, X2", "66 41 0f 38 41 d3"},
+	{"PHMINPOSUW X2, X11", "66 44 0f 38 41 da"},
+	{"PHMINPOSUW X2, X2", "66 0f 38 41 d2"},
+	{"PHSUBD (BX), X11", "66 44 0f 38 06 1b"},
+	{"PHSUBD (BX), X2", "66 0f 38 06 13"},
+	{"PHSUBD (R11), X11", "66 45 0f 38 06 1b"},
+	{"PHSUBD (R11), X2", "66 41 0f 38 06 13"},
+	{"PHSUBD X11, X11", "66 45 0f 38 06 db"},
+	{"PHSUBD X11, X2", "66 41 0f 38 06 d3"},
+	{"PHSUBD X2, X11", "66 44 0f 38 06 da"},
+	{"PHSUBD X2, X2", "66 0f 38 06 d2"},
+	{"PHSUBSW (BX), X11", "66 44 0f 38 07 1b"},
+	{"PHSUBSW (BX), X2", "66 0f 38 07 13"},
+	{"PHSUBSW (R11), X11", "66 45 0f 38 07 1b"},
+	{"PHSUBSW (R11), X2", "66 41 0f 38 07 13"},
+	{"PHSUBSW X11, X11", "66 45 0f 38 07 db"},
+	{"PHSUBSW X11, X2", "66 41 0f 38 07 d3"},
+	{"PHSUBSW X2, X11", "66 44 0f 38 07 da"},
+	{"PHSUBSW X2, X2", "66 0f 38 07 d2"},
+	{"PHSUBW (BX), X11", "66 44 0f 38 05 1b"},
+	{"PHSUBW (BX), X2", "66 0f 38 05 13"},
+	{"PHSUBW (R11), X11", "66 45 0f 38 05 1b"},
+	{"PHSUBW (R11), X2", "66 41 0f 38 05 13"},
+	{"PHSUBW X11, X11", "66 45 0f 38 05 db"},
+	{"PHSUBW X11, X2", "66 41 0f 38 05 d3"},
+	{"PHSUBW X2, X11", "66 44 0f 38 05 da"},
+	{"PHSUBW X2, X2", "66 0f 38 05 d2"},
+	{"PMADDUBSW (BX), X11", "66 44 0f 38 04 1b"},
+	{"PMADDUBSW (BX), X2", "66 0f 38 04 13"},
+	{"PMADDUBSW (R11), X11", "66 45 0f 38 04 1b"},
+	{"PMADDUBSW (R11), X2", "66 41 0f 38 04 13"},
+	{"PMADDUBSW X11, X11", "66 45 0f 38 04 db"},
+	{"PMADDUBSW X11, X2", "66 41 0f 38 04 d3"},
+	{"PMADDUBSW X2, X11", "66 44 0f 38 04 da"},
+	{"PMADDUBSW X2, X2", "66 0f 38 04 d2"},
+	{"PMADDWL (BX), M2", "0f f5 13"},
+	{"PMADDWL (BX), M3", "0f f5 1b"},
+	{"PMADDWL (BX), X11", "66 44 0f f5 1b"},
+	{"PMADDWL (BX), X2", "66 0f f5 13"},
+	{"PMADDWL (R11), M2", "41 0f f5 13"},
+	{"PMADDWL (R11), M3", "41 0f f5 1b"},
+	{"PMADDWL (R11), X11", "66 45 0f f5 1b"},
+	{"PMADDWL (R11), X2", "66 41 0f f5 13"},
+	{"PMADDWL M2, M2", "0f f5 d2"},
+	{"PMADDWL M2, M3", "0f f5 da"},
+	{"PMADDWL M3, M2", "0f f5 d3"},
+	{"PMADDWL M3, M3", "0f f5 db"},
+	{"PMADDWL X11, X11", "66 45 0f f5 db"},
+	{"PMADDWL X11, X2", "66 41 0f f5 d3"},
+	{"PMADDWL X2, X11", "66 44 0f f5 da"},
+	{"PMADDWL X2, X2", "66 0f f5 d2"},
+	{"PMAXSB (BX), X11", "66 44 0f 38 3c 1b"},
+	{"PMAXSB (BX), X2", "66 0f 38 3c 13"},
+	{"PMAXSB (R11), X11", "66 45 0f 38 3c 1b"},
+	{"PMAXSB (R11), X2", "66 41 0f 38 3c 13"},
+	{"PMAXSB X11, X11", "66 45 0f 38 3c db"},
+	{"PMAXSB X11, X2", "66 41 0f 38 3c d3"},
+	{"PMAXSB X2, X11", "66 44 0f 38 3c da"},
+	{"PMAXSB X2, X2", "66 0f 38 3c d2"},
+	{"PMAXSD (BX), X11", "66 44 0f 38 3d 1b"},
+	{"PMAXSD (BX), X2", "66 0f 38 3d 13"},
+	{"PMAXSD (R11), X11", "66 45 0f 38 3d 1b"},
+	{"PMAXSD (R11), X2", "66 41 0f 38 3d 13"},
+	{"PMAXSD X11, X11", "66 45 0f 38 3d db"},
+	{"PMAXSD X11, X2", "66 41 0f 38 3d d3"},
+	{"PMAXSD X2, X11", "66 44 0f 38 3d da"},
+	{"PMAXSD X2, X2", "66 0f 38 3d d2"},
+	{"PMAXSW (BX), X11", "66 44 0f ee 1b"},
+	{"PMAXSW (BX), X2", "66 0f ee 13"},
+	{"PMAXSW (R11), X11", "66 45 0f ee 1b"},
+	{"PMAXSW (R11), X2", "66 41 0f ee 13"},
+	{"PMAXSW X11, X11", "66 45 0f ee db"},
+	{"PMAXSW X11, X2", "66 41 0f ee d3"},
+	{"PMAXSW X2, X11", "66 44 0f ee da"},
+	{"PMAXSW X2, X2", "66 0f ee d2"},
+	{"PMAXUB (BX), X11", "66 44 0f de 1b"},
+	{"PMAXUB (BX), X2", "66 0f de 13"},
+	{"PMAXUB (R11), X11", "66 45 0f de 1b"},
+	{"PMAXUB (R11), X2", "66 41 0f de 13"},
+	{"PMAXUB X11, X11", "66 45 0f de db"},
+	{"PMAXUB X11, X2", "66 41 0f de d3"},
+	{"PMAXUB X2, X11", "66 44 0f de da"},
+	{"PMAXUB X2, X2", "66 0f de d2"},
+	{"PMAXUD (BX), X11", "66 44 0f 38 3f 1b"},
+	{"PMAXUD (BX), X2", "66 0f 38 3f 13"},
+	{"PMAXUD (R11), X11", "66 45 0f 38 3f 1b"},
+	{"PMAXUD (R11), X2", "66 41 0f 38 3f 13"},
+	{"PMAXUD X11, X11", "66 45 0f 38 3f db"},
+	{"PMAXUD X11, X2", "66 41 0f 38 3f d3"},
+	{"PMAXUD X2, X11", "66 44 0f 38 3f da"},
+	{"PMAXUD X2, X2", "66 0f 38 3f d2"},
+	{"PMAXUW (BX), X11", "66 44 0f 38 3e 1b"},
+	{"PMAXUW (BX), X2", "66 0f 38 3e 13"},
+	{"PMAXUW (R11), X11", "66 45 0f 38 3e 1b"},
+	{"PMAXUW (R11), X2", "66 41 0f 38 3e 13"},
+	{"PMAXUW X11, X11", "66 45 0f 38 3e db"},
+	{"PMAXUW X11, X2", "66 41 0f 38 3e d3"},
+	{"PMAXUW X2, X11", "66 44 0f 38 3e da"},
+	{"PMAXUW X2, X2", "66 0f 38 3e d2"},
+	{"PMINSB (BX), X11", "66 44 0f 38 38 1b"},
+	{"PMINSB (BX), X2", "66 0f 38 38 13"},
+	{"PMINSB (R11), X11", "66 45 0f 38 38 1b"},
+	{"PMINSB (R11), X2", "66 41 0f 38 38 13"},
+	{"PMINSB X11, X11", "66 45 0f 38 38 db"},
+	{"PMINSB X11, X2", "66 41 0f 38 38 d3"},
+	{"PMINSB X2, X11", "66 44 0f 38 38 da"},
+	{"PMINSB X2, X2", "66 0f 38 38 d2"},
+	{"PMINSD (BX), X11", "66 44 0f 38 39 1b"},
+	{"PMINSD (BX), X2", "66 0f 38 39 13"},
+	{"PMINSD (R11), X11", "66 45 0f 38 39 1b"},
+	{"PMINSD (R11), X2", "66 41 0f 38 39 13"},
+	{"PMINSD X11, X11", "66 45 0f 38 39 db"},
+	{"PMINSD X11, X2", "66 41 0f 38 39 d3"},
+	{"PMINSD X2, X11", "66 44 0f 38 39 da"},
+	{"PMINSD X2, X2", "66 0f 38 39 d2"},
+	{"PMINSW (BX), X11", "66 44 0f ea 1b"},
+	{"PMINSW (BX), X2", "66 0f ea 13"},
+	{"PMINSW (R11), X11", "66 45 0f ea 1b"},
+	{"PMINSW (R11), X2", "66 41 0f ea 13"},
+	{"PMINSW X11, X11", "66 45 0f ea db"},
+	{"PMINSW X11, X2", "66 41 0f ea d3"},
+	{"PMINSW X2, X11", "66 44 0f ea da"},
+	{"PMINSW X2, X2", "66 0f ea d2"},
+	{"PMINUB (BX), X11", "66 44 0f da 1b"},
+	{"PMINUB (BX), X2", "66 0f da 13"},
+	{"PMINUB (R11), X11", "66 45 0f da 1b"},
+	{"PMINUB (R11), X2", "66 41 0f da 13"},
+	{"PMINUB X11, X11", "66 45 0f da db"},
+	{"PMINUB X11, X2", "66 41 0f da d3"},
+	{"PMINUB X2, X11", "66 44 0f da da"},
+	{"PMINUB X2, X2", "66 0f da d2"},
+	{"PMINUD (BX), X11", "66 44 0f 38 3b 1b"},
+	{"PMINUD (BX), X2", "66 0f 38 3b 13"},
+	{"PMINUD (R11), X11", "66 45 0f 38 3b 1b"},
+	{"PMINUD (R11), X2", "66 41 0f 38 3b 13"},
+	{"PMINUD X11, X11", "66 45 0f 38 3b db"},
+	{"PMINUD X11, X2", "66 41 0f 38 3b d3"},
+	{"PMINUD X2, X11", "66 44 0f 38 3b da"},
+	{"PMINUD X2, X2", "66 0f 38 3b d2"},
+	{"PMINUW (BX), X11", "66 44 0f 38 3a 1b"},
+	{"PMINUW (BX), X2", "66 0f 38 3a 13"},
+	{"PMINUW (R11), X11", "66 45 0f 38 3a 1b"},
+	{"PMINUW (R11), X2", "66 41 0f 38 3a 13"},
+	{"PMINUW X11, X11", "66 45 0f 38 3a db"},
+	{"PMINUW X11, X2", "66 41 0f 38 3a d3"},
+	{"PMINUW X2, X11", "66 44 0f 38 3a da"},
+	{"PMINUW X2, X2", "66 0f 38 3a d2"},
+	{"PMOVMSKB M2, DX", "0f d7 d2"},
+	{"PMOVMSKB M2, R11", "44 0f d7 da"},
+	{"PMOVMSKB M3, DX", "0f d7 d3"},
+	{"PMOVMSKB M3, R11", "44 0f d7 db"},
+	{"PMOVMSKB X11, DX", "66 41 0f d7 d3"},
+	{"PMOVMSKB X11, R11", "66 45 0f d7 db"},
+	{"PMOVMSKB X2, DX", "66 0f d7 d2"},
+	{"PMOVMSKB X2, R11", "66 44 0f d7 da"},
+	{"PMOVSXBD (BX), X11", "66 44 0f 38 21 1b"},
+	{"PMOVSXBD (BX), X2", "66 0f 38 21 13"},
+	{"PMOVSXBD (R11), X11", "66 45 0f 38 21 1b"},
+	{"PMOVSXBD (R11), X2", "66 41 0f 38 21 13"},
+	{"PMOVSXBD X11, X11", "66 45 0f 38 21 db"},
+	{"PMOVSXBD X11, X2", "66 41 0f 38 21 d3"},
+	{"PMOVSXBD X2, X11", "66 44 0f 38 21 da"},
+	{"PMOVSXBD X2, X2", "66 0f 38 21 d2"},
+	{"PMOVSXBQ (BX), X11", "66 44 0f 38 22 1b"},
+	{"PMOVSXBQ (BX), X2", "66 0f 38 22 13"},
+	{"PMOVSXBQ (R11), X11", "66 45 0f 38 22 1b"},
+	{"PMOVSXBQ (R11), X2", "66 41 0f 38 22 13"},
+	{"PMOVSXBQ X11, X11", "66 45 0f 38 22 db"},
+	{"PMOVSXBQ X11, X2", "66 41 0f 38 22 d3"},
+	{"PMOVSXBQ X2, X11", "66 44 0f 38 22 da"},
+	{"PMOVSXBQ X2, X2", "66 0f 38 22 d2"},
+	{"PMOVSXBW (BX), X11", "66 44 0f 38 20 1b"},
+	{"PMOVSXBW (BX), X2", "66 0f 38 20 13"},
+	{"PMOVSXBW (R11), X11", "66 45 0f 38 20 1b"},
+	{"PMOVSXBW (R11), X2", "66 41 0f 38 20 13"},
+	{"PMOVSXBW X11, X11", "66 45 0f 38 20 db"},
+	{"PMOVSXBW X11, X2", "66 41 0f 38 20 d3"},
+	{"PMOVSXBW X2, X11", "66 44 0f 38 20 da"},
+	{"PMOVSXBW X2, X2", "66 0f 38 20 d2"},
+	{"PMOVSXDQ (BX), X11", "66 44 0f 38 25 1b"},
+	{"PMOVSXDQ (BX), X2", "66 0f 38 25 13"},
+	{"PMOVSXDQ (R11), X11", "66 45 0f 38 25 1b"},
+	{"PMOVSXDQ (R11), X2", "66 41 0f 38 25 13"},
+	{"PMOVSXDQ X11, X11", "66 45 0f 38 25 db"},
+	{"PMOVSXDQ X11, X2", "66 41 0f 38 25 d3"},
+	{"PMOVSXDQ X2, X11", "66 44 0f 38 25 da"},
+	{"PMOVSXDQ X2, X2", "66 0f 38 25 d2"},
+	{"PMOVSXWD (BX), X11", "66 44 0f 38 23 1b"},
+	{"PMOVSXWD (BX), X2", "66 0f 38 23 13"},
+	{"PMOVSXWD (R11), X11", "66 45 0f 38 23 1b"},
+	{"PMOVSXWD (R11), X2", "66 41 0f 38 23 13"},
+	{"PMOVSXWD X11, X11", "66 45 0f 38 23 db"},
+	{"PMOVSXWD X11, X2", "66 41 0f 38 23 d3"},
+	{"PMOVSXWD X2, X11", "66 44 0f 38 23 da"},
+	{"PMOVSXWD X2, X2", "66 0f 38 23 d2"},
+	{"PMOVSXWQ (BX), X11", "66 44 0f 38 24 1b"},
+	{"PMOVSXWQ (BX), X2", "66 0f 38 24 13"},
+	{"PMOVSXWQ (R11), X11", "66 45 0f 38 24 1b"},
+	{"PMOVSXWQ (R11), X2", "66 41 0f 38 24 13"},
+	{"PMOVSXWQ X11, X11", "66 45 0f 38 24 db"},
+	{"PMOVSXWQ X11, X2", "66 41 0f 38 24 d3"},
+	{"PMOVSXWQ X2, X11", "66 44 0f 38 24 da"},
+	{"PMOVSXWQ X2, X2", "66 0f 38 24 d2"},
+	{"PMOVZXBD (BX), X11", "66 44 0f 38 31 1b"},
+	{"PMOVZXBD (BX), X2", "66 0f 38 31 13"},
+	{"PMOVZXBD (R11), X11", "66 45 0f 38 31 1b"},
+	{"PMOVZXBD (R11), X2", "66 41 0f 38 31 13"},
+	{"PMOVZXBD X11, X11", "66 45 0f 38 31 db"},
+	{"PMOVZXBD X11, X2", "66 41 0f 38 31 d3"},
+	{"PMOVZXBD X2, X11", "66 44 0f 38 31 da"},
+	{"PMOVZXBD X2, X2", "66 0f 38 31 d2"},
+	{"PMOVZXBQ (BX), X11", "66 44 0f 38 32 1b"},
+	{"PMOVZXBQ (BX), X2", "66 0f 38 32 13"},
+	{"PMOVZXBQ (R11), X11", "66 45 0f 38 32 1b"},
+	{"PMOVZXBQ (R11), X2", "66 41 0f 38 32 13"},
+	{"PMOVZXBQ X11, X11", "66 45 0f 38 32 db"},
+	{"PMOVZXBQ X11, X2", "66 41 0f 38 32 d3"},
+	{"PMOVZXBQ X2, X11", "66 44 0f 38 32 da"},
+	{"PMOVZXBQ X2, X2", "66 0f 38 32 d2"},
+	{"PMOVZXBW (BX), X11", "66 44 0f 38 30 1b"},
+	{"PMOVZXBW (BX), X2", "66 0f 38 30 13"},
+	{"PMOVZXBW (R11), X11", "66 45 0f 38 30 1b"},
+	{"PMOVZXBW (R11), X2", "66 41 0f 38 30 13"},
+	{"PMOVZXBW X11, X11", "66 45 0f 38 30 db"},
+	{"PMOVZXBW X11, X2", "66 41 0f 38 30 d3"},
+	{"PMOVZXBW X2, X11", "66 44 0f 38 30 da"},
+	{"PMOVZXBW X2, X2", "66 0f 38 30 d2"},
+	{"PMOVZXDQ (BX), X11", "66 44 0f 38 35 1b"},
+	{"PMOVZXDQ (BX), X2", "66 0f 38 35 13"},
+	{"PMOVZXDQ (R11), X11", "66 45 0f 38 35 1b"},
+	{"PMOVZXDQ (R11), X2", "66 41 0f 38 35 13"},
+	{"PMOVZXDQ X11, X11", "66 45 0f 38 35 db"},
+	{"PMOVZXDQ X11, X2", "66 41 0f 38 35 d3"},
+	{"PMOVZXDQ X2, X11", "66 44 0f 38 35 da"},
+	{"PMOVZXDQ X2, X2", "66 0f 38 35 d2"},
+	{"PMOVZXWD (BX), X11", "66 44 0f 38 33 1b"},
+	{"PMOVZXWD (BX), X2", "66 0f 38 33 13"},
+	{"PMOVZXWD (R11), X11", "66 45 0f 38 33 1b"},
+	{"PMOVZXWD (R11), X2", "66 41 0f 38 33 13"},
+	{"PMOVZXWD X11, X11", "66 45 0f 38 33 db"},
+	{"PMOVZXWD X11, X2", "66 41 0f 38 33 d3"},
+	{"PMOVZXWD X2, X11", "66 44 0f 38 33 da"},
+	{"PMOVZXWD X2, X2", "66 0f 38 33 d2"},
+	{"PMOVZXWQ (BX), X11", "66 44 0f 38 34 1b"},
+	{"PMOVZXWQ (BX), X2", "66 0f 38 34 13"},
+	{"PMOVZXWQ (R11), X11", "66 45 0f 38 34 1b"},
+	{"PMOVZXWQ (R11), X2", "66 41 0f 38 34 13"},
+	{"PMOVZXWQ X11, X11", "66 45 0f 38 34 db"},
+	{"PMOVZXWQ X11, X2", "66 41 0f 38 34 d3"},
+	{"PMOVZXWQ X2, X11", "66 44 0f 38 34 da"},
+	{"PMOVZXWQ X2, X2", "66 0f 38 34 d2"},
+	{"PMULDQ (BX), X11", "66 44 0f 38 28 1b"},
+	{"PMULDQ (BX), X2", "66 0f 38 28 13"},
+	{"PMULDQ (R11), X11", "66 45 0f 38 28 1b"},
+	{"PMULDQ (R11), X2", "66 41 0f 38 28 13"},
+	{"PMULDQ X11, X11", "66 45 0f 38 28 db"},
+	{"PMULDQ X11, X2", "66 41 0f 38 28 d3"},
+	{"PMULDQ X2, X11", "66 44 0f 38 28 da"},
+	{"PMULDQ X2, X2", "66 0f 38 28 d2"},
+	{"PMULHRSW (BX), X11", "66 44 0f 38 0b 1b"},
+	{"PMULHRSW (BX), X2", "66 0f 38 0b 13"},
+	{"PMULHRSW (R11), X11", "66 45 0f 38 0b 1b"},
+	{"PMULHRSW (R11), X2", "66 41 0f 38 0b 13"},
+	{"PMULHRSW X11, X11", "66 45 0f 38 0b db"},
+	{"PMULHRSW X11, X2", "66 41 0f 38 0b d3"},
+	{"PMULHRSW X2, X11", "66 44 0f 38 0b da"},
+	{"PMULHRSW X2, X2", "66 0f 38 0b d2"},
+	{"PMULHUW (BX), M2", "0f e4 13"},
+	{"PMULHUW (BX), M3", "0f e4 1b"},
+	{"PMULHUW (BX), X11", "66 44 0f e4 1b"},
+	{"PMULHUW (BX), X2", "66 0f e4 13"},
+	{"PMULHUW (R11), M2", "41 0f e4 13"},
+	{"PMULHUW (R11), M3", "41 0f e4 1b"},
+	{"PMULHUW (R11), X11", "66 45 0f e4 1b"},
+	{"PMULHUW (R11), X2", "66 41 0f e4 13"},
+	{"PMULHUW M2, M2", "0f e4 d2"},
+	{"PMULHUW M2, M3", "0f e4 da"},
+	{"PMULHUW M3, M2", "0f e4 d3"},
+	{"PMULHUW M3, M3", "0f e4 db"},
+	{"PMULHUW X11, X11", "66 45 0f e4 db"},
+	{"PMULHUW X11, X2", "66 41 0f e4 d3"},
+	{"PMULHUW X2, X11", "66 44 0f e4 da"},
+	{"PMULHUW X2, X2", "66 0f e4 d2"},
+	{"PMULHW (BX), M2", "0f e5 13"},
+	{"PMULHW (BX), M3", "0f e5 1b"},
+	{"PMULHW (BX), X11", "66 44 0f e5 1b"},
+	{"PMULHW (BX), X2", "66 0f e5 13"},
+	{"PMULHW (R11), M2", "41 0f e5 13"},
+	{"PMULHW (R11), M3", "41 0f e5 1b"},
+	{"PMULHW (R11), X11", "66 45 0f e5 1b"},
+	{"PMULHW (R11), X2", "66 41 0f e5 13"},
+	{"PMULHW M2, M2", "0f e5 d2"},
+	{"PMULHW M2, M3", "0f e5 da"},
+	{"PMULHW M3, M2", "0f e5 d3"},
+	{"PMULHW M3, M3", "0f e5 db"},
+	{"PMULHW X11, X11", "66 45 0f e5 db"},
+	{"PMULHW X11, X2", "66 41 0f e5 d3"},
+	{"PMULHW X2, X11", "66 44 0f e5 da"},
+	{"PMULHW X2, X2", "66 0f e5 d2"},
+	{"PMULLD (BX), X11", "66 44 0f 38 40 1b"},
+	{"PMULLD (BX), X2", "66 0f 38 40 13"},
+	{"PMULLD (R11), X11", "66 45 0f 38 40 1b"},
+	{"PMULLD (R11), X2", "66 41 0f 38 40 13"},
+	{"PMULLD X11, X11", "66 45 0f 38 40 db"},
+	{"PMULLD X11, X2", "66 41 0f 38 40 d3"},
+	{"PMULLD X2, X11", "66 44 0f 38 40 da"},
+	{"PMULLD X2, X2", "66 0f 38 40 d2"},
+	{"PMULLW (BX), M2", "0f d5 13"},
+	{"PMULLW (BX), M3", "0f d5 1b"},
+	{"PMULLW (BX), X11", "66 44 0f d5 1b"},
+	{"PMULLW (BX), X2", "66 0f d5 13"},
+	{"PMULLW (R11), M2", "41 0f d5 13"},
+	{"PMULLW (R11), M3", "41 0f d5 1b"},
+	{"PMULLW (R11), X11", "66 45 0f d5 1b"},
+	{"PMULLW (R11), X2", "66 41 0f d5 13"},
+	{"PMULLW M2, M2", "0f d5 d2"},
+	{"PMULLW M2, M3", "0f d5 da"},
+	{"PMULLW M3, M2", "0f d5 d3"},
+	{"PMULLW M3, M3", "0f d5 db"},
+	{"PMULLW X11, X11", "66 45 0f d5 db"},
+	{"PMULLW X11, X2", "66 41 0f d5 d3"},
+	{"PMULLW X2, X11", "66 44 0f d5 da"},
+	{"PMULLW X2, X2", "66 0f d5 d2"},
+	{"PMULULQ (BX), M2", "0f f4 13"},
+	{"PMULULQ (BX), M3", "0f f4 1b"},
+	{"PMULULQ (BX), X11", "66 44 0f f4 1b"},
+	{"PMULULQ (BX), X2", "66 0f f4 13"},
+	{"PMULULQ (R11), M2", "41 0f f4 13"},
+	{"PMULULQ (R11), M3", "41 0f f4 1b"},
+	{"PMULULQ (R11), X11", "66 45 0f f4 1b"},
+	{"PMULULQ (R11), X2", "66 41 0f f4 13"},
+	{"PMULULQ M2, M2", "0f f4 d2"},
+	{"PMULULQ M2, M3", "0f f4 da"},
+	{"PMULULQ M3, M2", "0f f4 d3"},
+	{"PMULULQ M3, M3", "0f f4 db"},
+	{"PMULULQ X11, X11", "66 45 0f f4 db"},
+	{"PMULULQ X11, X2", "66 41 0f f4 d3"},
+	{"PMULULQ X2, X11", "66 44 0f f4 da"},
+	{"PMULULQ X2, X2", "66 0f f4 d2"},
+	{"PSADBW (BX), X11", "66 44 0f f6 1b"},
+	{"PSADBW (BX), X2", "66 0f f6 13"},
+	{"PSADBW (R11), X11", "66 45 0f f6 1b"},
+	{"PSADBW (R11), X2", "66 41 0f f6 13"},
+	{"PSADBW X11, X11", "66 45 0f f6 db"},
+	{"PSADBW X11, X2", "66 41 0f f6 d3"},
+	{"PSADBW X2, X11", "66 44 0f f6 da"},
+	{"PSADBW X2, X2", "66 0f f6 d2"},
+	{"PSHUFW $7, (BX), M2", "0f 70 13 07"},
+	{"PSHUFW $7, (BX), M3", "0f 70 1b 07"},
+	{"PSHUFW $7, (R11), M2", "41 0f 70 13 07"},
+	{"PSHUFW $7, (R11), M3", "41 0f 70 1b 07"},
+	{"PSHUFW $7, M2, M2", "0f 70 d2 07"},
+	{"PSHUFW $7, M2, M3", "0f 70 da 07"},
+	{"PSHUFW $7, M3, M2", "0f 70 d3 07"},
+	{"PSHUFW $7, M3, M3", "0f 70 db 07"},
+	{"PSIGNB (BX), X11", "66 44 0f 38 08 1b"},
+	{"PSIGNB (BX), X2", "66 0f 38 08 13"},
+	{"PSIGNB (R11), X11", "66 45 0f 38 08 1b"},
+	{"PSIGNB (R11), X2", "66 41 0f 38 08 13"},
+	{"PSIGNB X11, X11", "66 45 0f 38 08 db"},
+	{"PSIGNB X11, X2", "66 41 0f 38 08 d3"},
+	{"PSIGNB X2, X11", "66 44 0f 38 08 da"},
+	{"PSIGNB X2, X2", "66 0f 38 08 d2"},
+	{"PSIGND (BX), X11", "66 44 0f 38 0a 1b"},
+	{"PSIGND (BX), X2", "66 0f 38 0a 13"},
+	{"PSIGND (R11), X11", "66 45 0f 38 0a 1b"},
+	{"PSIGND (R11), X2", "66 41 0f 38 0a 13"},
+	{"PSIGND X11, X11", "66 45 0f 38 0a db"},
+	{"PSIGND X11, X2", "66 41 0f 38 0a d3"},
+	{"PSIGND X2, X11", "66 44 0f 38 0a da"},
+	{"PSIGND X2, X2", "66 0f 38 0a d2"},
+	{"PSIGNW (BX), X11", "66 44 0f 38 09 1b"},
+	{"PSIGNW (BX), X2", "66 0f 38 09 13"},
+	{"PSIGNW (R11), X11", "66 45 0f 38 09 1b"},
+	{"PSIGNW (R11), X2", "66 41 0f 38 09 13"},
+	{"PSIGNW X11, X11", "66 45 0f 38 09 db"},
+	{"PSIGNW X11, X2", "66 41 0f 38 09 d3"},
+	{"PSIGNW X2, X11", "66 44 0f 38 09 da"},
+	{"PSIGNW X2, X2", "66 0f 38 09 d2"},
+	{"PSLLL $7, M2", "0f 72 f2 07"},
+	{"PSLLL $7, M3", "0f 72 f3 07"},
+	{"PSLLL $7, X11", "66 41 0f 72 f3 07"},
+	{"PSLLL $7, X2", "66 0f 72 f2 07"},
+	{"PSLLL (BX), M2", "0f f2 13"},
+	{"PSLLL (BX), M3", "0f f2 1b"},
+	{"PSLLL (BX), X11", "66 44 0f f2 1b"},
+	{"PSLLL (BX), X2", "66 0f f2 13"},
+	{"PSLLL (R11), M2", "41 0f f2 13"},
+	{"PSLLL (R11), M3", "41 0f f2 1b"},
+	{"PSLLL (R11), X11", "66 45 0f f2 1b"},
+	{"PSLLL (R11), X2", "66 41 0f f2 13"},
+	{"PSLLL M2, M2", "0f f2 d2"},
+	{"PSLLL M2, M3", "0f f2 da"},
+	{"PSLLL M3, M2", "0f f2 d3"},
+	{"PSLLL M3, M3", "0f f2 db"},
+	{"PSLLL X11, X11", "66 45 0f f2 db"},
+	{"PSLLL X11, X2", "66 41 0f f2 d3"},
+	{"PSLLL X2, X11", "66 44 0f f2 da"},
+	{"PSLLL X2, X2", "66 0f f2 d2"},
+	{"PSLLO $7, X11", "66 41 0f 73 fb 07"},
+	{"PSLLO $7, X2", "66 0f 73 fa 07"},
+	{"PSLLQ $7, M2", "0f 73 f2 07"},
+	{"PSLLQ $7, M3", "0f 73 f3 07"},
+	{"PSLLQ $7, X11", "66 41 0f 73 f3 07"},
+	{"PSLLQ $7, X2", "66 0f 73 f2 07"},
+	{"PSLLQ (BX), M2", "0f f3 13"},
+	{"PSLLQ (BX), M3", "0f f3 1b"},
+	{"PSLLQ (BX), X11", "66 44 0f f3 1b"},
+	{"PSLLQ (BX), X2", "66 0f f3 13"},
+	{"PSLLQ (R11), M2", "41 0f f3 13"},
+	{"PSLLQ (R11), M3", "41 0f f3 1b"},
+	{"PSLLQ (R11), X11", "66 45 0f f3 1b"},
+	{"PSLLQ (R11), X2", "66 41 0f f3 13"},
+	{"PSLLQ M2, M2", "0f f3 d2"},
+	{"PSLLQ M2, M3", "0f f3 da"},
+	{"PSLLQ M3, M2", "0f f3 d3"},
+	{"PSLLQ M3, M3", "0f f3 db"},
+	{"PSLLQ X11, X11", "66 45 0f f3 db"},
+	{"PSLLQ X11, X2", "66 41 0f f3 d3"},
+	{"PSLLQ X2, X11", "66 44 0f f3 da"},
+	{"PSLLQ X2, X2", "66 0f f3 d2"},
+	{"PSLLW $7, M2", "0f 71 f2 07"},
+	{"PSLLW $7, M3", "0f 71 f3 07"},
+	{"PSLLW $7, X11", "66 41 0f 71 f3 07"},
+	{"PSLLW $7, X2", "66 0f 71 f2 07"},
+	{"PSLLW (BX), M2", "0f f1 13"},
+	{"PSLLW (BX), M3", "0f f1 1b"},
+	{"PSLLW (BX), X11", "66 44 0f f1 1b"},
+	{"PSLLW (BX), X2", "66 0f f1 13"},
+	{"PSLLW (R11), M2", "41 0f f1 13"},
+	{"PSLLW (R11), M3", "41 0f f1 1b"},
+	{"PSLLW (R11), X11", "66 45 0f f1 1b"},
+	{"PSLLW (R11), X2", "66 41 0f f1 13"},
+	{"PSLLW M2, M2", "0f f1 d2"},
+	{"PSLLW M2, M3", "0f f1 da"},
+	{"PSLLW M3, M2", "0f f1 d3"},
+	{"PSLLW M3, M3", "0f f1 db"},
+	{"PSLLW X11, X11", "66 45 0f f1 db"},
+	{"PSLLW X11, X2", "66 41 0f f1 d3"},
+	{"PSLLW X2, X11", "66 44 0f f1 da"},
+	{"PSLLW X2, X2", "66 0f f1 d2"},
+	{"PSRAL $7, M2", "0f 72 e2 07"},
+	{"PSRAL $7, M3", "0f 72 e3 07"},
+	{"PSRAL $7, X11", "66 41 0f 72 e3 07"},
+	{"PSRAL $7, X2", "66 0f 72 e2 07"},
+	{"PSRAL (BX), M2", "0f e2 13"},
+	{"PSRAL (BX), M3", "0f e2 1b"},
+	{"PSRAL (BX), X11", "66 44 0f e2 1b"},
+	{"PSRAL (BX), X2", "66 0f e2 13"},
+	{"PSRAL (R11), M2", "41 0f e2 13"},
+	{"PSRAL (R11), M3", "41 0f e2 1b"},
+	{"PSRAL (R11), X11", "66 45 0f e2 1b"},
+	{"PSRAL (R11), X2", "66 41 0f e2 13"},
+	{"PSRAL M2, M2", "0f e2 d2"},
+	{"PSRAL M2, M3", "0f e2 da"},
+	{"PSRAL M3, M2", "0f e2 d3"},
+	{"PSRAL M3, M3", "0f e2 db"},
+	{"PSRAL X11, X11", "66 45 0f e2 db"},
+	{"PSRAL X11, X2", "66 41 0f e2 d3"},
+	{"PSRAL X2, X11", "66 44 0f e2 da"},
+	{"PSRAL X2, X2", "66 0f e2 d2"},
+	{"PSRAW $7, M2", "0f 71 e2 07"},
+	{"PSRAW $7, M3", "0f 71 e3 07"},
+	{"PSRAW $7, X11", "66 41 0f 71 e3 07"},
+	{"PSRAW $7, X2", "66 0f 71 e2 07"},
+	{"PSRAW (BX), M2", "0f e1 13"},
+	{"PSRAW (BX), M3", "0f e1 1b"},
+	{"PSRAW (BX), X11", "66 44 0f e1 1b"},
+	{"PSRAW (BX), X2", "66 0f e1 13"},
+	{"PSRAW (R11), M2", "41 0f e1 13"},
+	{"PSRAW (R11), M3", "41 0f e1 1b"},
+	{"PSRAW (R11), X11", "66 45 0f e1 1b"},
+	{"PSRAW (R11), X2", "66 41 0f e1 13"},
+	{"PSRAW M2, M2", "0f e1 d2"},
+	{"PSRAW M2, M3", "0f e1 da"},
+	{"PSRAW M3, M2", "0f e1 d3"},
+	{"PSRAW M3, M3", "0f e1 db"},
+	{"PSRAW X11, X11", "66 45 0f e1 db"},
+	{"PSRAW X11, X2", "66 41 0f e1 d3"},
+	{"PSRAW X2, X11", "66 44 0f e1 da"},
+	{"PSRAW X2, X2", "66 0f e1 d2"},
+	{"PSRLL $7, M2", "0f 72 d2 07"},
+	{"PSRLL $7, M3", "0f 72 d3 07"},
+	{"PSRLL $7, X11", "66 41 0f 72 d3 07"},
+	{"PSRLL $7, X2", "66 0f 72 d2 07"},
+	{"PSRLL (BX), M2", "0f d2 13"},
+	{"PSRLL (BX), M3", "0f d2 1b"},
+	{"PSRLL (BX), X11", "66 44 0f d2 1b"},
+	{"PSRLL (BX), X2", "66 0f d2 13"},
+	{"PSRLL (R11), M2", "41 0f d2 13"},
+	{"PSRLL (R11), M3", "41 0f d2 1b"},
+	{"PSRLL (R11), X11", "66 45 0f d2 1b"},
+	{"PSRLL (R11), X2", "66 41 0f d2 13"},
+	{"PSRLL M2, M2", "0f d2 d2"},
+	{"PSRLL M2, M3", "0f d2 da"},
+	{"PSRLL M3, M2", "0f d2 d3"},
+	{"PSRLL M3, M3", "0f d2 db"},
+	{"PSRLL X11, X11", "66 45 0f d2 db"},
+	{"PSRLL X11, X2", "66 41 0f d2 d3"},
+	{"PSRLL X2, X11", "66 44 0f d2 da"},
+	{"PSRLL X2, X2", "66 0f d2 d2"},
+	{"PSRLO $7, X11", "66 41 0f 73 db 07"},
+	{"PSRLO $7, X2", "66 0f 73 da 07"},
+	{"PSRLQ $7, M2", "0f 73 d2 07"},
+	{"PSRLQ $7, M3", "0f 73 d3 07"},
+	{"PSRLQ $7, X11", "66 41 0f 73 d3 07"},
+	{"PSRLQ $7, X2", "66 0f 73 d2 07"},
+	{"PSRLQ (BX), M2", "0f d3 13"},
+	{"PSRLQ (BX), M3", "0f d3 1b"},
+	{"PSRLQ (BX), X11", "66 44 0f d3 1b"},
+	{"PSRLQ (BX), X2", "66 0f d3 13"},
+	{"PSRLQ (R11), M2", "41 0f d3 13"},
+	{"PSRLQ (R11), M3", "41 0f d3 1b"},
+	{"PSRLQ (R11), X11", "66 45 0f d3 1b"},
+	{"PSRLQ (R11), X2", "66 41 0f d3 13"},
+	{"PSRLQ M2, M2", "0f d3 d2"},
+	{"PSRLQ M2, M3", "0f d3 da"},
+	{"PSRLQ M3, M2", "0f d3 d3"},
+	{"PSRLQ M3, M3", "0f d3 db"},
+	{"PSRLQ X11, X11", "66 45 0f d3 db"},
+	{"PSRLQ X11, X2", "66 41 0f d3 d3"},
+	{"PSRLQ X2, X11", "66 44 0f d3 da"},
+	{"PSRLQ X2, X2", "66 0f d3 d2"},
+	{"PSRLW $7, M2", "0f 71 d2 07"},
+	{"PSRLW $7, M3", "0f 71 d3 07"},
+	{"PSRLW $7, X11", "66 41 0f 71 d3 07"},
+	{"PSRLW $7, X2", "66 0f 71 d2 07"},
+	{"PSRLW (BX), M2", "0f d1 13"},
+	{"PSRLW (BX), M3", "0f d1 1b"},
+	{"PSRLW (BX), X11", "66 44 0f d1 1b"},
+	{"PSRLW (BX), X2", "66 0f d1 13"},
+	{"PSRLW (R11), M2", "41 0f d1 13"},
+	{"PSRLW (R11), M3", "41 0f d1 1b"},
+	{"PSRLW (R11), X11", "66 45 0f d1 1b"},
+	{"PSRLW (R11), X2", "66 41 0f d1 13"},
+	{"PSRLW M2, M2", "0f d1 d2"},
+	{"PSRLW M2, M3", "0f d1 da"},
+	{"PSRLW M3, M2", "0f d1 d3"},
+	{"PSRLW M3, M3", "0f d1 db"},
+	{"PSRLW X11, X11", "66 45 0f d1 db"},
+	{"PSRLW X11, X2", "66 41 0f d1 d3"},
+	{"PSRLW X2, X11", "66 44 0f d1 da"},
+	{"PSRLW X2, X2", "66 0f d1 d2"},
+	{"PSUBSB (BX), X11", "66 44 0f e8 1b"},
+	{"PSUBSB (BX), X2", "66 0f e8 13"},
+	{"PSUBSB (R11), X11", "66 45 0f e8 1b"},
+	{"PSUBSB (R11), X2", "66 41 0f e8 13"},
+	{"PSUBSB X11, X11", "66 45 0f e8 db"},
+	{"PSUBSB X11, X2", "66 41 0f e8 d3"},
+	{"PSUBSB X2, X11", "66 44 0f e8 da"},
+	{"PSUBSB X2, X2", "66 0f e8 d2"},
+	{"PSUBSW (BX), X11", "66 44 0f e9 1b"},
+	{"PSUBSW (BX), X2", "66 0f e9 13"},
+	{"PSUBSW (R11), X11", "66 45 0f e9 1b"},
+	{"PSUBSW (R11), X2", "66 41 0f e9 13"},
+	{"PSUBSW X11, X11", "66 45 0f e9 db"},
+	{"PSUBSW X11, X2", "66 41 0f e9 d3"},
+	{"PSUBSW X2, X11", "66 44 0f e9 da"},
+	{"PSUBSW X2, X2", "66 0f e9 d2"},
+	{"PSUBUSB (BX), X11", "66 44 0f d8 1b"},
+	{"PSUBUSB (BX), X2", "66 0f d8 13"},
+	{"PSUBUSB (R11), X11", "66 45 0f d8 1b"},
+	{"PSUBUSB (R11), X2", "66 41 0f d8 13"},
+	{"PSUBUSB X11, X11", "66 45 0f d8 db"},
+	{"PSUBUSB X11, X2", "66 41 0f d8 d3"},
+	{"PSUBUSB X2, X11", "66 44 0f d8 da"},
+	{"PSUBUSB X2, X2", "66 0f d8 d2"},
+	{"PSUBUSW (BX), X11", "66 44 0f d9 1b"},
+	{"PSUBUSW (BX), X2", "66 0f d9 13"},
+	{"PSUBUSW (R11), X11", "66 45 0f d9 1b"},
+	{"PSUBUSW (R11), X2", "66 41 0f d9 13"},
+	{"PSUBUSW X11, X11", "66 45 0f d9 db"},
+	{"PSUBUSW X11, X2", "66 41 0f d9 d3"},
+	{"PSUBUSW X2, X11", "66 44 0f d9 da"},
+	{"PSUBUSW X2, X2", "66 0f d9 d2"},
+	{"PTEST (BX), X11", "66 44 0f 38 17 1b"},
+	{"PTEST (BX), X2", "66 0f 38 17 13"},
+	{"PTEST (R11), X11", "66 45 0f 38 17 1b"},
+	{"PTEST (R11), X2", "66 41 0f 38 17 13"},
+	{"PTEST X11, X11", "66 45 0f 38 17 db"},
+	{"PTEST X11, X2", "66 41 0f 38 17 d3"},
+	{"PTEST X2, X11", "66 44 0f 38 17 da"},
+	{"PTEST X2, X2", "66 0f 38 17 d2"},
+	{"PUNPCKHBW (BX), M2", "0f 68 13"},
+	{"PUNPCKHBW (BX), M3", "0f 68 1b"},
+	{"PUNPCKHBW (BX), X11", "66 44 0f 68 1b"},
+	{"PUNPCKHBW (BX), X2", "66 0f 68 13"},
+	{"PUNPCKHBW (R11), M2", "41 0f 68 13"},
+	{"PUNPCKHBW (R11), M3", "41 0f 68 1b"},
+	{"PUNPCKHBW (R11), X11", "66 45 0f 68 1b"},
+	{"PUNPCKHBW (R11), X2", "66 41 0f 68 13"},
+	{"PUNPCKHBW M2, M2", "0f 68 d2"},
+	{"PUNPCKHBW M2, M3", "0f 68 da"},
+	{"PUNPCKHBW M3, M2", "0f 68 d3"},
+	{"PUNPCKHBW M3, M3", "0f 68 db"},
+	{"PUNPCKHBW X11, X11", "66 45 0f 68 db"},
+	{"PUNPCKHBW X11, X2", "66 41 0f 68 d3"},
+	{"PUNPCKHBW X2, X11", "66 44 0f 68 da"},
+	{"PUNPCKHBW X2, X2", "66 0f 68 d2"},
+	{"PUNPCKHLQ (BX), M2", "0f 6a 13"},
+	{"PUNPCKHLQ (BX), M3", "0f 6a 1b"},
+	{"PUNPCKHLQ (BX), X11", "66 44 0f 6a 1b"},
+	{"PUNPCKHLQ (BX), X2", "66 0f 6a 13"},
+	{"PUNPCKHLQ (R11), M2", "41 0f 6a 13"},
+	{"PUNPCKHLQ (R11), M3", "41 0f 6a 1b"},
+	{"PUNPCKHLQ (R11), X11", "66 45 0f 6a 1b"},
+	{"PUNPCKHLQ (R11), X2", "66 41 0f 6a 13"},
+	{"PUNPCKHLQ M2, M2", "0f 6a d2"},
+	{"PUNPCKHLQ M2, M3", "0f 6a da"},
+	{"PUNPCKHLQ M3, M2", "0f 6a d3"},
+	{"PUNPCKHLQ M3, M3", "0f 6a db"},
+	{"PUNPCKHLQ X11, X11", "66 45 0f 6a db"},
+	{"PUNPCKHLQ X11, X2", "66 41 0f 6a d3"},
+	{"PUNPCKHLQ X2, X11", "66 44 0f 6a da"},
+	{"PUNPCKHLQ X2, X2", "66 0f 6a d2"},
+	{"PUNPCKHQDQ (BX), X11", "66 44 0f 6d 1b"},
+	{"PUNPCKHQDQ (BX), X2", "66 0f 6d 13"},
+	{"PUNPCKHQDQ (R11), X11", "66 45 0f 6d 1b"},
+	{"PUNPCKHQDQ (R11), X2", "66 41 0f 6d 13"},
+	{"PUNPCKHQDQ X11, X11", "66 45 0f 6d db"},
+	{"PUNPCKHQDQ X11, X2", "66 41 0f 6d d3"},
+	{"PUNPCKHQDQ X2, X11", "66 44 0f 6d da"},
+	{"PUNPCKHQDQ X2, X2", "66 0f 6d d2"},
+	{"PUNPCKHWL (BX), M2", "0f 69 13"},
+	{"PUNPCKHWL (BX), M3", "0f 69 1b"},
+	{"PUNPCKHWL (BX), X11", "66 44 0f 69 1b"},
+	{"PUNPCKHWL (BX), X2", "66 0f 69 13"},
+	{"PUNPCKHWL (R11), M2", "41 0f 69 13"},
+	{"PUNPCKHWL (R11), M3", "41 0f 69 1b"},
+	{"PUNPCKHWL (R11), X11", "66 45 0f 69 1b"},
+	{"PUNPCKHWL (R11), X2", "66 41 0f 69 13"},
+	{"PUNPCKHWL M2, M2", "0f 69 d2"},
+	{"PUNPCKHWL M2, M3", "0f 69 da"},
+	{"PUNPCKHWL M3, M2", "0f 69 d3"},
+	{"PUNPCKHWL M3, M3", "0f 69 db"},
+	{"PUNPCKHWL X11, X11", "66 45 0f 69 db"},
+	{"PUNPCKHWL X11, X2", "66 41 0f 69 d3"},
+	{"PUNPCKHWL X2, X11", "66 44 0f 69 da"},
+	{"PUNPCKHWL X2, X2", "66 0f 69 d2"},
+	{"PUNPCKLLQ (BX), M2", "0f 62 13"},
+	{"PUNPCKLLQ (BX), M3", "0f 62 1b"},
+	{"PUNPCKLLQ (BX), X11", "66 44 0f 62 1b"},
+	{"PUNPCKLLQ (BX), X2", "66 0f 62 13"},
+	{"PUNPCKLLQ (R11), M2", "41 0f 62 13"},
+	{"PUNPCKLLQ (R11), M3", "41 0f 62 1b"},
+	{"PUNPCKLLQ (R11), X11", "66 45 0f 62 1b"},
+	{"PUNPCKLLQ (R11), X2", "66 41 0f 62 13"},
+	{"PUNPCKLLQ M2, M2", "0f 62 d2"},
+	{"PUNPCKLLQ M2, M3", "0f 62 da"},
+	{"PUNPCKLLQ M3, M2", "0f 62 d3"},
+	{"PUNPCKLLQ M3, M3", "0f 62 db"},
+	{"PUNPCKLLQ X11, X11", "66 45 0f 62 db"},
+	{"PUNPCKLLQ X11, X2", "66 41 0f 62 d3"},
+	{"PUNPCKLLQ X2, X11", "66 44 0f 62 da"},
+	{"PUNPCKLLQ X2, X2", "66 0f 62 d2"},
+	{"PUNPCKLQDQ (BX), X11", "66 44 0f 6c 1b"},
+	{"PUNPCKLQDQ (BX), X2", "66 0f 6c 13"},
+	{"PUNPCKLQDQ (R11), X11", "66 45 0f 6c 1b"},
+	{"PUNPCKLQDQ (R11), X2", "66 41 0f 6c 13"},
+	{"PUNPCKLQDQ X11, X11", "66 45 0f 6c db"},
+	{"PUNPCKLQDQ X11, X2", "66 41 0f 6c d3"},
+	{"PUNPCKLQDQ X2, X11", "66 44 0f 6c da"},
+	{"PUNPCKLQDQ X2, X2", "66 0f 6c d2"},
+	{"PUNPCKLWL (BX), M2", "0f 61 13"},
+	{"PUNPCKLWL (BX), M3", "0f 61 1b"},
+	{"PUNPCKLWL (BX), X11", "66 44 0f 61 1b"},
+	{"PUNPCKLWL (BX), X2", "66 0f 61 13"},
+	{"PUNPCKLWL (R11), M2", "41 0f 61 13"},
+	{"PUNPCKLWL (R11), M3", "41 0f 61 1b"},
+	{"PUNPCKLWL (R11), X11", "66 45 0f 61 1b"},
+	{"PUNPCKLWL (R11), X2", "66 41 0f 61 13"},
+	{"PUNPCKLWL M2, M2", "0f 61 d2"},
+	{"PUNPCKLWL M2, M3", "0f 61 da"},
+	{"PUNPCKLWL M3, M2", "0f 61 d3"},
+	{"PUNPCKLWL M3, M3", "0f 61 db"},
+	{"PUNPCKLWL X11, X11", "66 45 0f 61 db"},
+	{"PUNPCKLWL X11, X2", "66 41 0f 61 d3"},
+	{"PUNPCKLWL X2, X11", "66 44 0f 61 da"},
+	{"PUNPCKLWL X2, X2", "66 0f 61 d2"},
+	{"RCPPS (BX), X11", "44 0f 53 1b"},
+	{"RCPPS (BX), X2", "0f 53 13"},
+	{"RCPPS (R11), X11", "45 0f 53 1b"},
+	{"RCPPS (R11), X2", "41 0f 53 13"},
+	{"RCPPS X11, X11", "45 0f 53 db"},
+	{"RCPPS X11, X2", "41 0f 53 d3"},
+	{"RCPPS X2, X11", "44 0f 53 da"},
+	{"RCPPS X2, X2", "0f 53 d2"},
+	{"RCPSS (BX), X11", "f3 44 0f 53 1b"},
+	{"RCPSS (BX), X2", "f3 0f 53 13"},
+	{"RCPSS (R11), X11", "f3 45 0f 53 1b"},
+	{"RCPSS (R11), X2", "f3 41 0f 53 13"},
+	{"RCPSS X11, X11", "f3 45 0f 53 db"},
+	{"RCPSS X11, X2", "f3 41 0f 53 d3"},
+	{"RCPSS X2, X11", "f3 44 0f 53 da"},
+	{"RCPSS X2, X2", "f3 0f 53 d2"},
+	{"ROUNDPD $7, (BX), X11", "66 44 0f 3a 09 1b 07"},
+	{"ROUNDPD $7, (BX), X2", "66 0f 3a 09 13 07"},
+	{"ROUNDPD $7, (R11), X11", "66 45 0f 3a 09 1b 07"},
+	{"ROUNDPD $7, (R11), X2", "66 41 0f 3a 09 13 07"},
+	{"ROUNDPD $7, X11, X11", "66 45 0f 3a 09 db 07"},
+	{"ROUNDPD $7, X11, X2", "66 41 0f 3a 09 d3 07"},
+	{"ROUNDPD $7, X2, X11", "66 44 0f 3a 09 da 07"},
+	{"ROUNDPD $7, X2, X2", "66 0f 3a 09 d2 07"},
+	{"ROUNDPS $7, (BX), X11", "66 44 0f 3a 08 1b 07"},
+	{"ROUNDPS $7, (BX), X2", "66 0f 3a 08 13 07"},
+	{"ROUNDPS $7, (R11), X11", "66 45 0f 3a 08 1b 07"},
+	{"ROUNDPS $7, (R11), X2", "66 41 0f 3a 08 13 07"},
+	{"ROUNDPS $7, X11, X11", "66 45 0f 3a 08 db 07"},
+	{"ROUNDPS $7, X11, X2", "66 41 0f 3a 08 d3 07"},
+	{"ROUNDPS $7, X2, X11", "66 44 0f 3a 08 da 07"},
+	{"ROUNDPS $7, X2, X2", "66 0f 3a 08 d2 07"},
+	{"ROUNDSD $7, (BX), X11", "66 44 0f 3a 0b 1b 07"},
+	{"ROUNDSD $7, (BX), X2", "66 0f 3a 0b 13 07"},
+	{"ROUNDSD $7, (R11), X11", "66 45 0f 3a 0b 1b 07"},
+	{"ROUNDSD $7, (R11), X2", "66 41 0f 3a 0b 13 07"},
+	{"ROUNDSD $7, X11, X11", "66 45 0f 3a 0b db 07"},
+	{"ROUNDSD $7, X11, X2", "66 41 0f 3a 0b d3 07"},
+	{"ROUNDSD $7, X2, X11", "66 44 0f 3a 0b da 07"},
+	{"ROUNDSD $7, X2, X2", "66 0f 3a 0b d2 07"},
+	{"ROUNDSS $7, (BX), X11", "66 44 0f 3a 0a 1b 07"},
+	{"ROUNDSS $7, (BX), X2", "66 0f 3a 0a 13 07"},
+	{"ROUNDSS $7, (R11), X11", "66 45 0f 3a 0a 1b 07"},
+	{"ROUNDSS $7, (R11), X2", "66 41 0f 3a 0a 13 07"},
+	{"ROUNDSS $7, X11, X11", "66 45 0f 3a 0a db 07"},
+	{"ROUNDSS $7, X11, X2", "66 41 0f 3a 0a d3 07"},
+	{"ROUNDSS $7, X2, X11", "66 44 0f 3a 0a da 07"},
+	{"ROUNDSS $7, X2, X2", "66 0f 3a 0a d2 07"},
+	{"RSQRTPS (BX), X11", "44 0f 52 1b"},
+	{"RSQRTPS (BX), X2", "0f 52 13"},
+	{"RSQRTPS (R11), X11", "45 0f 52 1b"},
+	{"RSQRTPS (R11), X2", "41 0f 52 13"},
+	{"RSQRTPS X11, X11", "45 0f 52 db"},
+	{"RSQRTPS X11, X2", "41 0f 52 d3"},
+	{"RSQRTPS X2, X11", "44 0f 52 da"},
+	{"RSQRTPS X2, X2", "0f 52 d2"},
+	{"RSQRTSS (BX), X11", "f3 44 0f 52 1b"},
+	{"RSQRTSS (BX), X2", "f3 0f 52 13"},
+	{"RSQRTSS (R11), X11", "f3 45 0f 52 1b"},
+	{"RSQRTSS (R11), X2", "f3 41 0f 52 13"},
+	{"RSQRTSS X11, X11", "f3 45 0f 52 db"},
+	{"RSQRTSS X11, X2", "f3 41 0f 52 d3"},
+	{"RSQRTSS X2, X11", "f3 44 0f 52 da"},
+	{"RSQRTSS X2, X2", "f3 0f 52 d2"},
+	{"SQRTPD (BX), X11", "66 44 0f 51 1b"},
+	{"SQRTPD (BX), X2", "66 0f 51 13"},
+	{"SQRTPD (R11), X11", "66 45 0f 51 1b"},
+	{"SQRTPD (R11), X2", "66 41 0f 51 13"},
+	{"SQRTPD X11, X11", "66 45 0f 51 db"},
+	{"SQRTPD X11, X2", "66 41 0f 51 d3"},
+	{"SQRTPD X2, X11", "66 44 0f 51 da"},
+	{"SQRTPD X2, X2", "66 0f 51 d2"},
+	{"SQRTPS (BX), X11", "44 0f 51 1b"},
+	{"SQRTPS (BX), X2", "0f 51 13"},
+	{"SQRTPS (R11), X11", "45 0f 51 1b"},
+	{"SQRTPS (R11), X2", "41 0f 51 13"},
+	{"SQRTPS X11, X11", "45 0f 51 db"},
+	{"SQRTPS X11, X2", "41 0f 51 d3"},
+	{"SQRTPS X2, X11", "44 0f 51 da"},
+	{"SQRTPS X2, X2", "0f 51 d2"},
+	{"SQRTSS (BX), X11", "f3 44 0f 51 1b"},
+	{"SQRTSS (BX), X2", "f3 0f 51 13"},
+	{"SQRTSS (R11), X11", "f3 45 0f 51 1b"},
+	{"SQRTSS (R11), X2", "f3 41 0f 51 13"},
+	{"SQRTSS X11, X11", "f3 45 0f 51 db"},
+	{"SQRTSS X11, X2", "f3 41 0f 51 d3"},
+	{"SQRTSS X2, X11", "f3 44 0f 51 da"},
+	{"SQRTSS X2, X2", "f3 0f 51 d2"},
+	{"UCOMISD (BX), X11", "66 44 0f 2e 1b"},
+	{"UCOMISD (BX), X2", "66 0f 2e 13"},
+	{"UCOMISD (R11), X11", "66 45 0f 2e 1b"},
+	{"UCOMISD (R11), X2", "66 41 0f 2e 13"},
+	{"UCOMISD X11, X11", "66 45 0f 2e db"},
+	{"UCOMISD X11, X2", "66 41 0f 2e d3"},
+	{"UCOMISD X2, X11", "66 44 0f 2e da"},
+	{"UCOMISD X2, X2", "66 0f 2e d2"},
+	{"UCOMISS (BX), X11", "44 0f 2e 1b"},
+	{"UCOMISS (BX), X2", "0f 2e 13"},
+	{"UCOMISS (R11), X11", "45 0f 2e 1b"},
+	{"UCOMISS (R11), X2", "41 0f 2e 13"},
+	{"UCOMISS X11, X11", "45 0f 2e db"},
+	{"UCOMISS X11, X2", "41 0f 2e d3"},
+	{"UCOMISS X2, X11", "44 0f 2e da"},
+	{"UCOMISS X2, X2", "0f 2e d2"},
+}
+
+// TestAmd64SseCorpus assembles every corpus line and requires the same bytes
+// go tool asm emits for it.
+func TestAmd64SseCorpus(t *testing.T) {
+	for _, tc := range amd64SseCorpus {
+		fn := firstText(t, "TEXT ·p(SB), 4, $0\n\t"+tc.line+"\n")
+		code, _, err := Assemble(fn)
+		if err != nil {
+			t.Errorf("%s: %v", tc.line, err)
+			continue
+		}
+		if got := hexBytes(code); got != tc.want {
+			t.Errorf("%s: got %s, want %s", tc.line, got, tc.want)
+		}
+	}
+}
diff --git a/asm/amd64_system.go b/asm/amd64_system.go
index e8d30e9..eb27259 100644
--- a/asm/amd64_system.go
+++ b/asm/amd64_system.go
@@ -53,6 +53,10 @@ var systemNoOperand = map[string][]byte{
 	"SYSEXIT":    {0x0F, 0x35},
 	"SYSEXIT64":  {0x48, 0x0F, 0x35},
 	"SYSRET":     {0x0F, 0x07},
+	"LEAVE":      {0xC9},
+	"LEAVEQ":     {0xC9},
+	"XEND":       {0x0F, 0x01, 0xD5},
+	"XTEST":      {0x0F, 0x01, 0xD6},
 	"CBW":        {0x66, 0x98},
 	"CWDE":       {0x98},
 	"CDQE":       {0x48, 0x98},
@@ -253,6 +257,40 @@ func (e *enc) encodeSystem(upper string, ops []Operand) (bool, error) {
 		}
 		return true, e.emit(i)
 	}
+	// INVPCID invalidates a translation-cache entry: 66 0F38 82 with the
+	// type in a general register and the descriptor in memory.
+	if upper == "INVPCID" {
+		if len(ops) != 2 {
+			return true, fmt.Errorf("INVPCID expects 2 operands, got %d", len(ops))
+		}
+		if !isX86Mem(ops[0]) {
+			return true, fmt.Errorf("INVPCID requires a memory descriptor first")
+		}
+		srcReg, ok := ops[1].(Reg)
+		if !ok || srcReg.isVec() {
+			return true, fmt.Errorf("INVPCID: the second operand must be a general register")
+		}
+		i := &instr{prefix: 0x66, opcode: []byte{0x0F, 0x38, 0x82}, modrm: -1, sib: -1}
+		if err := setRM(i, srcReg, ops[0], 8); err != nil {
+			return true, err
+		}
+		return true, e.emit(i)
+	}
+	// XABORT carries its imm8 status byte in the C6 F8 group form.
+	if upper == "XABORT" {
+		if len(ops) != 1 {
+			return true, fmt.Errorf("XABORT expects 1 immediate operand, got %d", len(ops))
+		}
+		imm, ok := ops[0].(Imm)
+		if !ok {
+			return true, fmt.Errorf("XABORT requires an immediate")
+		}
+		immByte, err := imm8(int64(imm))
+		if err != nil {
+			return true, err
+		}
+		return true, e.emit(&instr{opcode: []byte{0xC6, 0xF8}, modrm: -1, sib: -1, imm: []byte{immByte}})
+	}
 	return false, nil
 }
 
diff --git a/asm/instrs.go b/asm/instrs.go
index e22f030..63b7ede 100644
--- a/asm/instrs.go
+++ b/asm/instrs.go
@@ -182,13 +182,24 @@ func (e *enc) encodeMov(ops []Operand, size int) error {
 
 	// MMX register moves: MOVQ M0, mem and MOVQ mem, M0 are the MMX
 	// load/store pair 0F 6F/0F 7F (no prefix); a register pair takes the
-	// load opcode.  The XMM MOVQ forms follow below.
+	// load opcode.  The GPR crossings ride the MOVD opcodes with REX.W
+	// (0F 6E into the bank, 0F 7E out), and an XMM source crosses into the
+	// bank through the F2 0F D6 move.  The XMM MOVQ forms follow below.
 	if m, ok := src.(Reg); ok && m.mmx {
 		switch d := dst.(type) {
 		case Reg:
-			if !d.mmx {
+			if !d.mmx && (d.isVec() || d.fp) {
 				return fmt.Errorf("MOV: MMX register moves stay inside the M bank")
 			}
+			if !d.mmx {
+				// M → GPR: 0F 7E with REX.W, the bank in reg and the GPR in
+				// r/m, the store layout the toolchain picks.
+				i := &instr{opcode: []byte{0x0F, 0x7E}, modrm: -1, sib: -1, rexW: true}
+				if err := setRM(i, m, d, 8); err != nil {
+					return err
+				}
+				return e.emit(i)
+			}
 			i := &instr{opcode: []byte{0x0F, 0x6F}, modrm: -1, sib: -1}
 			if err := setRM(i, d, src, 8); err != nil {
 				return err
@@ -204,15 +215,30 @@ func (e *enc) encodeMov(ops []Operand, size int) error {
 		return fmt.Errorf("MOV: invalid MMX destination")
 	}
 	if m, ok := dst.(Reg); ok && m.mmx {
-		srcM, ok := src.(Mem)
-		if !ok {
-			return fmt.Errorf("MOV: MMX load takes a memory source")
+		switch src.(type) {
+		case Mem, sbMem:
+			i := &instr{opcode: []byte{0x0F, 0x6F}, modrm: -1, sib: -1}
+			if err := setRM(i, m, src, 8); err != nil {
+				return err
+			}
+			return e.emit(i)
+		case Reg:
+			if g := src.(Reg); g.isVec() {
+				// X → M: F2 0F D6, the bank in reg, the XMM source in r/m.
+				i := &instr{prefix: 0xF2, opcode: []byte{0x0F, 0xD6}, modrm: -1, sib: -1}
+				if err := setRM(i, m, src, 8); err != nil {
+					return err
+				}
+				return e.emit(i)
+			}
+			// GPR → M: 0F 6E with REX.W, the bank in reg, the GPR in r/m.
+			i := &instr{opcode: []byte{0x0F, 0x6E}, modrm: -1, sib: -1, rexW: true}
+			if err := setRM(i, m, src, 8); err != nil {
+				return err
+			}
+			return e.emit(i)
 		}
-		i := &instr{opcode: []byte{0x0F, 0x6F}, modrm: -1, sib: -1}
-		if err := setRM(i, m, srcM, 8); err != nil {
-			return err
-		}
-		return e.emit(i)
+		return fmt.Errorf("MOV: MMX load takes a register or memory source")
 	}
 
 	if srcVec || dstVec {
@@ -323,14 +349,14 @@ func (e *enc) encodeMov(ops []Operand, size int) error {
 	case Imm:
 		if dstIsReg {
 			v := int64(src)
-			// The Go assembler compresses 64-bit moves whose immediate fits
-			// a signed int32, choosing per sign:
+			// The Go assembler compresses 64-bit moves whose immediate
+			// fits the zero-extending 32-bit span, choosing per sign:
 			//   v >= 0: B8+rd imm32 without REX.W (zero-extended by the
 			//           hardware, REX.B still emitted for R8-R15);
 			//   v <  0: REX.W C7 /0 imm32 (sign-extended, the plain B8+rd
 			//           form would zero-extend and corrupt the value).
 			// Out-of-range immediates keep the B8+rd imm64 form.
-			if size == 8 && v >= 0 && v <= (1<<31)-1 {
+			if size == 8 && v >= 0 && v <= (1<<32)-1 {
 				i := newInstr(4, []byte{0xB8 + byte(dstReg.idx&7)})
 				i.rexB = dstReg.idx >= 8
 				i.imm = le32(v)