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feat(arch): the SVE2.1 Z-alias permutations and copies

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Assisted-by: GLM 5.3 Flash
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petrbalvin committed 2026-10-07 02:27:35 +02:00
1 parent 8231302bca
commit 6c4932c4ec
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+1142 -10
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asm/arm64_ext_asm_test.go
+103
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@@ -321,3 +321,106 @@ func TestArm64AssembleExtensionLeavesScalarsAlone(t *testing.T) {
}
}
}
// TestArm64AssembleExtensionStage2Golden drives the SVE2.1 Z-alias
// statements through the full assembler: corpus text in, corpus word out.
// The statements carry the spellings the layer reads: dot and slash
// qualifiers, bare predicates, bare vectors, general registers and the
// immediate-with-source alias.
func TestArm64AssembleExtensionStage2Golden(t *testing.T) {
tests := []struct {
stmt string
want uint32
}{
{"ZABS Z7.D, P4.M, Z13.D", 0x04d6b0ed},
{"ZABS Z7.D, P4.Z, Z13.D", 0x04c6b0ed},
{"ZADD Z15.B, Z0.B, P3.M, Z0.B", 0x04000de0},
{"ZADD Z7.D, Z23.D, Z13.D", 0x04e702ed},
{"ZAND Z15.B, Z0.B, P3.M, Z0.B", 0x041a0de0},
{"ZAND Z7.D, Z6.D, Z23.D", 0x042730d7},
{"ZBIC Z15.B, Z0.B, P3.M, Z0.B", 0x041b0de0},
{"ZBIC Z7.D, Z6.D, Z23.D", 0x04e730d7},
{"ZCLS Z7.D, P4.M, Z13.D", 0x04d8b0ed},
{"ZCLS Z7.D, P4.Z, Z13.D", 0x04c8b0ed},
{"ZCLZ Z7.D, P4.M, Z13.D", 0x04d9b0ed},
{"ZCLZ Z7.D, P4.Z, Z13.D", 0x04c9b0ed},
{"ZCOMPACT Z7.D, P4, Z13.D", 0x05e190ed},
{"ZCOMPACT Z7.D, P4, Z13.D", 0x05e190ed},
{"ZEOR Z15.B, Z0.B, P3.M, Z0.B", 0x04190de0},
{"ZEOR Z7.D, Z6.D, Z23.D", 0x04a730d7},
{"ZEXPAND Z7.D, P4, Z13.D", 0x05f190ed},
{"ZMOVPRFX Z7.D, P4.Z, Z21.D", 0x04d030f5},
{"ZMOVPRFX Z11, Z6", 0x0420bd66},
{"ZNEG Z7.D, P4.M, Z13.D", 0x04d7b0ed},
{"ZNEG Z7.D, P4.Z, Z13.D", 0x04c7b0ed},
{"ZNOT Z7.D, P4.M, Z13.D", 0x04deb0ed},
{"ZNOT Z7.D, P4.Z, Z13.D", 0x04ceb0ed},
{"ZORR Z15.B, Z0.B, P3.M, Z0.B", 0x04180de0},
{"ZORR Z7.D, Z6.D, Z23.D", 0x046730d7},
{"ZREV Z1.S, Z26.S", 0x05b8383a},
{"ZREVB Z7.D, P4.M, Z13.D", 0x05e490ed},
{"ZREVB Z7.D, P4.Z, Z13.D", 0x05e4b0ed},
{"ZREVD Z13.Q, P1.M, Z22.Q", 0x052e85b6},
{"ZREVD Z13.Q, P1.Z, Z22.Q", 0x052ea5b6},
{"ZREVH Z7.D, P4.M, Z13.D", 0x05e590ed},
{"ZREVH Z7.D, P4.Z, Z13.D", 0x05e5b0ed},
{"ZREVW Z13.D, P1.M, Z22.D", 0x05e685b6},
{"ZREVW Z13.D, P1.Z, Z22.D", 0x05e6a5b6},
{"ZSEL Z23.B, Z21.B, P14, Z2.B", 0x0537faa2},
{"ZSQABS Z7.D, P4.M, Z13.D", 0x44c8b0ed},
{"ZSQABS Z7.D, P4.Z, Z13.D", 0x44cab0ed},
{"ZSQNEG Z7.D, P4.M, Z13.D", 0x44c9b0ed},
{"ZSQNEG Z7.D, P4.Z, Z13.D", 0x44cbb0ed},
{"ZSUB Z15.B, Z0.B, P3.M, Z0.B", 0x04010de0},
{"ZSUB Z7.D, Z23.D, Z13.D", 0x04e706ed},
{"ZSUBR Z15.B, Z0.B, P3.M, Z0.B", 0x04030de0},
{"ZSUNPKHI Z15.B, Z0.H", 0x057139e0},
{"ZSUNPKLO Z15.B, Z0.H", 0x057039e0},
{"ZSXTB Z7.D, P4.M, Z13.D", 0x04d0b0ed},
{"ZSXTB Z7.D, P4.Z, Z13.D", 0x04c0b0ed},
{"ZSXTH Z7.D, P4.M, Z13.D", 0x04d2b0ed},
{"ZSXTH Z7.D, P4.Z, Z13.D", 0x04c2b0ed},
{"ZSXTW Z13.D, P1.M, Z22.D", 0x04d4a5b6},
{"ZSXTW Z13.D, P1.Z, Z22.D", 0x04c4a5b6},
{"ZTBX Z7.D, Z23.D, Z13.D", 0x05e72eed},
{"ZTBXQ Z7.D, Z23.D, Z13.D", 0x05e736ed},
{"ZTRN1 Z7.D, Z23.D, Z13.D", 0x05e772ed},
{"ZTRN1 Z7.Q, Z6.Q, Z23.Q", 0x05a718d7},
{"ZTRN2 Z7.D, Z23.D, Z13.D", 0x05e776ed},
{"ZTRN2 Z7.Q, Z6.Q, Z23.Q", 0x05a71cd7},
{"ZUUNPKHI Z15.B, Z0.H", 0x057339e0},
{"ZUUNPKLO Z15.B, Z0.H", 0x057239e0},
{"ZUXTB Z7.D, P4.M, Z13.D", 0x04d1b0ed},
{"ZUXTB Z7.D, P4.Z, Z13.D", 0x04c1b0ed},
{"ZUXTH Z7.D, P4.M, Z13.D", 0x04d3b0ed},
{"ZUXTH Z7.D, P4.Z, Z13.D", 0x04c3b0ed},
{"ZUXTW Z13.D, P1.M, Z22.D", 0x04d5a5b6},
{"ZUXTW Z13.D, P1.Z, Z22.D", 0x04c5a5b6},
{"ZUZP1 Z7.D, Z23.D, Z13.D", 0x05e76aed},
{"ZUZP1 Z7.Q, Z6.Q, Z23.Q", 0x05a708d7},
{"ZUZP2 Z7.D, Z23.D, Z13.D", 0x05e76eed},
{"ZUZP2 Z7.Q, Z6.Q, Z23.Q", 0x05a70cd7},
{"ZUZPQ1 Z7.D, Z23.D, Z13.D", 0x44c7eaed},
{"ZUZPQ2 Z7.D, Z23.D, Z13.D", 0x44c7eeed},
{"ZZIP1 Z7.D, Z23.D, Z13.D", 0x05e762ed},
{"ZZIP1 Z7.Q, Z6.Q, Z23.Q", 0x05a700d7},
{"ZZIP2 Z7.D, Z23.D, Z13.D", 0x05e766ed},
{"ZZIP2 Z7.Q, Z6.Q, Z23.Q", 0x05a704d7},
{"ZZIPQ1 Z7.D, Z23.D, Z13.D", 0x44c7e2ed},
{"ZZIPQ2 Z7.D, Z23.D, Z13.D", 0x44c7e6ed},
{"ZDUP R2, Z10.D", 0x05e0384a},
{"ZINSR R2, Z10.D", 0x05e4384a},
{"ZADD $6, Z7.D, Z7.D", 0x25e0c0c7},
{"ZSUB $6, Z7.D, Z7.D", 0x25e1c0c7},
{"ZSUBR $6, Z7.D, Z7.D", 0x25e3c0c7},
}
for _, tt := range tests {
words := assembleArm64Words(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")
if len(words) != 2 {
t.Fatalf("%s: got %d words, want the statement and RET", tt.stmt, len(words))
}
if words[0] != tt.want {
t.Errorf("%s:\n got %08x\n want %08x", tt.stmt, words[0], tt.want)
}
}
}