feat(asm): extend arm64 encoder with FP, conditional select, CRC32 and tests
Assisted-by: MiMo V2.5 Pro
This commit is contained in:
@@ -0,0 +1,59 @@
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// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
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// SPDX-License-Identifier: BSD-3-Clause
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package asm
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import (
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"strings"
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"testing"
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"sourcedock.dev/petrbalvin/gasm-devkit/parser"
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)
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// TestGOObjectAARCH64Structure checks the basic structure of the emitted
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// AArch64 GOOBJ: the preamble, the magic, the block offsets and the
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// non-package symbol definitions.
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func TestGOObjectAARCH64Structure(t *testing.T) {
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f, errs := parser.Parse("k_arm64.s", `
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#include "textflag.h"
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TEXT ·add(SB), NOSPLIT, $0-24
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MOVD a+0(FP), R4
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MOVD b+8(FP), R5
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ADD R5, R4, R4
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MOVD R4, ret+16(FP)
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RET
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`)
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if len(errs) > 0 {
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t.Fatalf("parse: %v", errs)
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}
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img, err := AssembleFileARM64(f)
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if err != nil {
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t.Fatalf("AssembleFileARM64: %v", err)
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}
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obj, err := img.GOObjectAARCH64("testpkg", "k_arm64.s")
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if err != nil {
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t.Fatalf("GOObjectAARCH64: %v", err)
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}
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// Check preamble.
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idx := strings.Index(string(obj), "\n!\n")
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if idx < 0 {
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t.Fatal("missing preamble separator")
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}
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preamble := string(obj[:idx])
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if !strings.HasPrefix(preamble, "go object") {
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t.Errorf("preamble = %q, want 'go object ...'", preamble)
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}
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// Check GOOBJ magic.
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magicIdx := idx + 3
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if magicIdx+8 > len(obj) || string(obj[magicIdx:magicIdx+8]) != "\x00go120ld" {
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t.Error("missing GOOBJ magic")
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}
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// The object should contain the function's code.
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if len(img.Code) == 0 {
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t.Error("no code generated")
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}
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}
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+302
-9
@@ -218,6 +218,51 @@ func encodeARM64Instr(instr *ast.Instr, pc int, offsets map[string]int, fi arm64
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return encodeARM64DPSR(mnem, enc.op, ops)
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}
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// FP 3-operand (Rm, Rn, Rd).
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if enc, ok := a64InstrTable[mnem]; ok && enc.format == a64FFP3 {
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return encodeARM64FP3(mnem, enc.op, ops)
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}
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// FP unary (Rn, Rd).
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if enc, ok := a64InstrTable[mnem]; ok && enc.format == a64FFPUnary {
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return encodeARM64FPUnary(mnem, enc.op, ops)
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}
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// FP 4-operand FMA (Ra, Rm, Rn, Rd).
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if enc, ok := a64InstrTable[mnem]; ok && enc.format == a64FFP4 {
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return encodeARM64FP4(mnem, enc.op, ops)
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}
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// FP compare (Rm, Rn or #0, Rn).
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if enc, ok := a64InstrTable[mnem]; ok && enc.format == a64FFPCmp {
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return encodeARM64FPCmp(mnem, enc.op, ops)
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}
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// FP conditional compare (Rm, Rn, #nzcv, cond).
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if enc, ok := a64InstrTable[mnem]; ok && enc.format == a64FFPCCmp {
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return encodeARM64FPCCmp(mnem, enc.op, ops)
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}
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// FP conditional select (Rm, Rn, Rd, cond).
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if enc, ok := a64InstrTable[mnem]; ok && enc.format == a64FFPSel {
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return encodeARM64FPSel(mnem, enc.op, ops)
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}
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// FP ↔ integer conversion.
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if enc, ok := a64InstrTable[mnem]; ok && enc.format == a64FFPCvt {
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return encodeARM64FPCvt(mnem, enc.op, ops)
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}
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// Conditional select (CSEL, CSINC, CSINV, CSNEG, CSET, CSETM, CINC, CINV, CNEG).
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if enc, ok := a64InstrTable[mnem]; ok && enc.format == a64FCSEL {
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return encodeARM64CSEL(mnem, enc.op, ops)
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}
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// CRC32.
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if enc, ok := a64InstrTable[mnem]; ok && enc.format == a64FCRC32 {
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return encodeARM64CRC32(mnem, enc.op, ops)
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}
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return nil, fmt.Errorf("unsupported arm64 instruction %q", mnem)
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}
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@@ -621,7 +666,11 @@ func arm64Bitmask(v uint64, sf int) (N, immr, imms uint32, ok bool) {
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return
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}
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// encodeARM64RegMove encodes a register-to-register move as ORR Rd, ZR, Rs.
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// encodeARM64RegMove encodes a register-to-register move.
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// Integer → integer: ORR Rd, ZR, Rs.
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// FP → FP: FMOV Fd, Fn (FP data processing).
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// FP ↔ GP: FMOV general (FPCVTI encoding).
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// Go Plan 9 syntax: MOV dst, src (first operand = destination).
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func encodeARM64RegMove(mnem string, src, dst *ast.Operand) ([]byte, error) {
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rs := arm64RegNum(operandRegName(src))
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rd := arm64RegNum(operandRegName(dst))
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@@ -631,21 +680,37 @@ func encodeARM64RegMove(mnem string, src, dst *ast.Operand) ([]byte, error) {
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sc := arm64RegClassOf(operandRegName(src))
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dc := arm64RegClassOf(operandRegName(dst))
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// FP → FP: FMOV Rd, Rs
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// FP → FP: FMOV Fd, Fn (FP data processing unary form).
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if sc == arm64ClsFP && dc == arm64ClsFP {
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sf := uint32(1) // 64-bit
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if mnem == "FMOVS" {
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sf = 0
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}
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// FMOV: 0x1E<<24 | type<<22 | 1<<21 | 0x10<<10 | Rm<<5 | Rd
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typ := uint32(1) // 64-bit double
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if mnem == "FMOVS" {
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typ = 0 // 32-bit float
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}
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return a64wordLE(sf<<31 | 0x1E<<24 | typ<<22 | 1<<21 | 0x10<<10 | uint32(rs)<<5 | uint32(rd)), nil
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// FPOP1S encoding: 0x1E204000 | type<<22 | Rn<<5 | Rd
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return a64wordLE(0x1E<<24 | typ<<22 | 1<<21 | 0x10<<10 | uint32(rs)<<5 | uint32(rd)), nil
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}
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// Integer → integer: ORR Rd, ZR, Rs
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// GP ↔ FP: FMOV general (FPCVTI encoding).
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// Go syntax: FMOV FPdst, GPsrc or FMOV GPdst, FPsrc.
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// First operand = destination, second = source.
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if sc == arm64ClsFP && dc == arm64ClsGR {
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// FP → GP: FMOV Wd/Xd, Sn/Dn. opcode bits[20:16]=6.
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sf, typ := uint32(0), uint32(0)
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if mnem == "FMOVD" {
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sf, typ = 1, 1
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}
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return a64wordLE(sf<<31 | 0x1E<<24 | typ<<22 | 1<<21 | 6<<16 | uint32(rs)<<5 | uint32(rd)), nil
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}
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if sc == arm64ClsGR && dc == arm64ClsFP {
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// GP → FP: FMOV Vd, Wn/Xn. opcode bits[20:16]=7.
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sf, typ := uint32(0), uint32(0)
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if mnem == "FMOVD" {
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sf, typ = 1, 1
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}
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return a64wordLE(sf<<31 | 0x1E<<24 | typ<<22 | 1<<21 | 7<<16 | uint32(rs)<<5 | uint32(rd)), nil
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}
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// Integer → integer: ORR Rd, ZR, Rs.
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sf := uint32(1) // 64-bit
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if mnem == "MOVW" || mnem == "MOVWU" || mnem == "MOVB" || mnem == "MOVBU" ||
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mnem == "MOVH" || mnem == "MOVHU" {
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@@ -775,6 +840,234 @@ func arm64Label(op *ast.Operand) string {
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return op.Raw
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}
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// ---- FP instruction encoding ----
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// encodeARM64FP3 encodes a FP 3-operand instruction (Rm, Rn, Rd).
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// FADD, FSUB, FMUL, FDIV, FMAX, FMIN, FNMUL.
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func encodeARM64FP3(mnem string, baseOp uint32, ops []*ast.Operand) ([]byte, error) {
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if len(ops) != 3 {
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return nil, fmt.Errorf("%s expects 3 operands, got %d", mnem, len(ops))
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}
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rm := arm64RegNum(operandRegName(ops[0]))
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rn := arm64RegNum(operandRegName(ops[1]))
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rd := arm64RegNum(operandRegName(ops[2]))
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if rm < 0 || rn < 0 || rd < 0 {
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return nil, fmt.Errorf("invalid register operand in %s", mnem)
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}
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return a64wordLE(baseOp | uint32(rm)<<16 | uint32(rn)<<5 | uint32(rd)), nil
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}
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// encodeARM64FPUnary encodes a FP unary instruction (Rn, Rd).
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// FMOV reg-reg, FABS, FNEG, FSQRT, FCVT cross-precision, FRINT*.
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func encodeARM64FPUnary(mnem string, baseOp uint32, ops []*ast.Operand) ([]byte, error) {
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if len(ops) != 2 {
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return nil, fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
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}
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rn := arm64RegNum(operandRegName(ops[0]))
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rd := arm64RegNum(operandRegName(ops[1]))
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if rn < 0 || rd < 0 {
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return nil, fmt.Errorf("invalid register operand in %s", mnem)
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}
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return a64wordLE(baseOp | uint32(rn)<<5 | uint32(rd)), nil
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}
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// encodeARM64FP4 encodes a FP 4-operand FMA instruction (Ra, Rm, Rn, Rd).
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// FMADD, FMSUB, FNMADD, FNMSUB.
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func encodeARM64FP4(mnem string, baseOp uint32, ops []*ast.Operand) ([]byte, error) {
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var ra, rm, rn, rd int
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switch len(ops) {
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case 4:
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ra = arm64RegNum(operandRegName(ops[0]))
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rm = arm64RegNum(operandRegName(ops[1]))
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rn = arm64RegNum(operandRegName(ops[2]))
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rd = arm64RegNum(operandRegName(ops[3]))
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case 3:
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// 3-operand form: Fa, Fm, Fd → Fd = Fa ± Fd*Fm (Rn = Rd)
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ra = arm64RegNum(operandRegName(ops[0]))
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rm = arm64RegNum(operandRegName(ops[1]))
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rd = arm64RegNum(operandRegName(ops[2]))
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rn = rd
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default:
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return nil, fmt.Errorf("%s expects 3 or 4 operands, got %d", mnem, len(ops))
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}
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if ra < 0 || rm < 0 || rn < 0 || rd < 0 {
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return nil, fmt.Errorf("invalid register operand in %s", mnem)
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}
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return a64wordLE(baseOp | uint32(ra)<<16 | uint32(rm)<<10 | uint32(rn)<<5 | uint32(rd)), nil
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}
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// encodeARM64FPCmp encodes a FP compare instruction.
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// Go assembler syntax: FCMP Fn, Fm (register) or FCMP $0.0, Fn (compare with zero).
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// ARM64 encoding: Rm in bits[20:16], Rn in bits[9:5].
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// Go puts first operand → Rm, second → Rn.
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func encodeARM64FPCmp(mnem string, baseOp uint32, ops []*ast.Operand) ([]byte, error) {
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if len(ops) != 2 {
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return nil, fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
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}
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// Check if first operand is #0 (compare with zero): FCMP $0.0, Fn.
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if isImmOperand(ops[0]) && immFromOperand(ops[0]) == 0 {
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rn := arm64RegNum(operandRegName(ops[1]))
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if rn < 0 {
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return nil, fmt.Errorf("invalid register operand in %s", mnem)
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}
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// For compare with zero: Rm=0, op2 bit 3 set (|= 8).
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return a64wordLE((baseOp | 8) | 0<<16 | uint32(rn)<<5), nil
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}
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// Register compare: FCMP Fn, Fm.
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// Go puts first operand in Rm field, second in Rn field.
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rm := arm64RegNum(operandRegName(ops[0]))
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rn := arm64RegNum(operandRegName(ops[1]))
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if rm < 0 || rn < 0 {
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return nil, fmt.Errorf("invalid register operand in %s", mnem)
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}
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return a64wordLE(baseOp | uint32(rm)<<16 | uint32(rn)<<5), nil
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}
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// encodeARM64FPCCmp encodes a FP conditional compare.
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// Go assembler syntax: FCCMP cond, Fn, Fm, $nzcv
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// ARM64 encoding: Rm in bits[20:16], Rn in bits[9:5].
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// Go puts ops[1] in Rm field, ops[2] in Rn field.
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func encodeARM64FPCCmp(mnem string, baseOp uint32, ops []*ast.Operand) ([]byte, error) {
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if len(ops) != 4 {
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return nil, fmt.Errorf("%s expects 4 operands, got %d", mnem, len(ops))
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}
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condName := operandRegName(ops[0])
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cond, ok := arm64CondMap[condName]
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if !ok {
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return nil, fmt.Errorf("invalid condition code %q in %s", condName, mnem)
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}
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// Go puts ops[1] in Rm (bits 20:16), ops[2] in Rn (bits 9:5).
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rm := arm64RegNum(operandRegName(ops[1]))
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rn := arm64RegNum(operandRegName(ops[2]))
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if rm < 0 || rn < 0 {
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return nil, fmt.Errorf("invalid register operand in %s", mnem)
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}
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nzcv := uint32(immFromOperand(ops[3]))
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return a64wordLE(baseOp | uint32(rm)<<16 | cond<<12 | uint32(rn)<<5 | nzcv&0xF), nil
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}
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// encodeARM64FPSel encodes a FP conditional select.
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// Go assembler syntax: FCSEL cond, Fn, Fm, Fd
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func encodeARM64FPSel(mnem string, baseOp uint32, ops []*ast.Operand) ([]byte, error) {
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if len(ops) != 4 {
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return nil, fmt.Errorf("%s expects 4 operands, got %d", mnem, len(ops))
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}
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// Operand order: cond, Fn, Fm, Fd
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condName := operandRegName(ops[0])
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cond, ok := arm64CondMap[condName]
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if !ok {
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return nil, fmt.Errorf("invalid condition code %q in %s", condName, mnem)
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}
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rn := arm64RegNum(operandRegName(ops[1]))
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rm := arm64RegNum(operandRegName(ops[2]))
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rd := arm64RegNum(operandRegName(ops[3]))
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if rn < 0 || rm < 0 || rd < 0 {
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return nil, fmt.Errorf("invalid register operand in %s", mnem)
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}
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return a64wordLE(baseOp | uint32(rm)<<16 | cond<<12 | uint32(rn)<<5 | uint32(rd)), nil
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}
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// encodeARM64FPCvt encodes a FP ↔ integer conversion instruction.
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// The operand order depends on direction: FCVTZS Fd, Rn (FP→int) or SCVTF Rd, Fn (int→FP).
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func encodeARM64FPCvt(mnem string, baseOp uint32, ops []*ast.Operand) ([]byte, error) {
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if len(ops) != 2 {
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return nil, fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
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}
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src := arm64RegNum(operandRegName(ops[0]))
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dst := arm64RegNum(operandRegName(ops[1]))
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if src < 0 || dst < 0 {
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return nil, fmt.Errorf("invalid register operand in %s", mnem)
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}
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return a64wordLE(baseOp | uint32(src)<<5 | uint32(dst)), nil
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}
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// encodeARM64CSEL encodes a conditional select instruction.
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// CSEL Rm, Rn, Rd, cond (4 operands) or CSET Rd, cond (2 operands).
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func encodeARM64CSEL(mnem string, baseOp uint32, ops []*ast.Operand) ([]byte, error) {
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isAlias := mnem == "CSET" || mnem == "CSETW" || mnem == "CSETM" || mnem == "CSETMW" ||
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mnem == "CINC" || mnem == "CINCW" || mnem == "CINV" || mnem == "CINVW" ||
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mnem == "CNEG" || mnem == "CNEGW"
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if isAlias {
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is2op := mnem == "CSET" || mnem == "CSETW" || mnem == "CSETM" || mnem == "CSETMW"
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if is2op {
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// CSET cond, Rd → CSEL XZR, XZR, Rd, inverted_cond
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if len(ops) != 2 {
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return nil, fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
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}
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condName := operandRegName(ops[0])
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cond, ok := arm64CondMap[condName]
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if !ok {
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return nil, fmt.Errorf("invalid condition code %q in %s", condName, mnem)
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}
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rd := arm64RegNum(operandRegName(ops[1]))
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if rd < 0 {
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return nil, fmt.Errorf("invalid register operand in %s", mnem)
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}
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invCond := cond ^ 1
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return a64wordLE(baseOp | 31<<16 | invCond<<12 | 31<<5 | uint32(rd)), nil
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}
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// CINC cond, Rn, Rd → CSINC Rn, Rn, Rd, inverted_cond
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if len(ops) != 3 {
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return nil, fmt.Errorf("%s expects 3 operands, got %d", mnem, len(ops))
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}
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condName := operandRegName(ops[0])
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cond, ok := arm64CondMap[condName]
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if !ok {
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return nil, fmt.Errorf("invalid condition code %q in %s", condName, mnem)
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}
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rn := arm64RegNum(operandRegName(ops[1]))
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rd := arm64RegNum(operandRegName(ops[2]))
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if rn < 0 || rd < 0 {
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return nil, fmt.Errorf("invalid register operand in %s", mnem)
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}
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invCond := cond ^ 1
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return a64wordLE(baseOp | uint32(rn)<<16 | invCond<<12 | uint32(rn)<<5 | uint32(rd)), nil
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}
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// CSEL cond, Rn, Rm, Rd (4 operands) — condition first.
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// Go assembler syntax: CSEL cond, Rn, Rm, Rd
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// ARM64 encoding: Rm in bits[20:16], Rn in bits[9:5], Rd in bits[4:0].
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if len(ops) != 4 {
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return nil, fmt.Errorf("%s expects 4 operands, got %d", mnem, len(ops))
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}
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condName := operandRegName(ops[0])
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cond, ok := arm64CondMap[condName]
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if !ok {
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return nil, fmt.Errorf("invalid condition code %q in %s", condName, mnem)
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}
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rn := arm64RegNum(operandRegName(ops[1]))
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rm := arm64RegNum(operandRegName(ops[2]))
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rd := arm64RegNum(operandRegName(ops[3]))
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if rn < 0 || rm < 0 || rd < 0 {
|
||||
return nil, fmt.Errorf("invalid register operand in %s", mnem)
|
||||
}
|
||||
return a64wordLE(baseOp | uint32(rm)<<16 | cond<<12 | uint32(rn)<<5 | uint32(rd)), nil
|
||||
}
|
||||
|
||||
// encodeARM64CRC32 encodes a CRC32 instruction.
|
||||
// Go assembler syntax: CRC32B Rm, Rd (2 operands, Rn=Rd).
|
||||
func encodeARM64CRC32(mnem string, baseOp uint32, ops []*ast.Operand) ([]byte, error) {
|
||||
if len(ops) == 3 {
|
||||
// 3-operand form: CRC32B Rm, Rn, Rd → use Rm and Rd, Rn=Rd.
|
||||
rm := arm64RegNum(operandRegName(ops[0]))
|
||||
rd := arm64RegNum(operandRegName(ops[2]))
|
||||
if rm < 0 || rd < 0 {
|
||||
return nil, fmt.Errorf("invalid register operand in %s", mnem)
|
||||
}
|
||||
return a64wordLE(baseOp | uint32(rm)<<16 | uint32(rd)<<5 | uint32(rd)), nil
|
||||
}
|
||||
if len(ops) != 2 {
|
||||
return nil, fmt.Errorf("%s expects 2 or 3 operands, got %d", mnem, len(ops))
|
||||
}
|
||||
rm := arm64RegNum(operandRegName(ops[0]))
|
||||
rd := arm64RegNum(operandRegName(ops[1]))
|
||||
if rm < 0 || rd < 0 {
|
||||
return nil, fmt.Errorf("invalid register operand in %s", mnem)
|
||||
}
|
||||
return a64wordLE(baseOp | uint32(rm)<<16 | uint32(rd)<<5 | uint32(rd)), nil
|
||||
}
|
||||
|
||||
// AssembleFileARM64 assembles every TEXT function of a parsed arm64 file
|
||||
// and lays out its static symbols (GLOBL/DATA) in a data section behind the
|
||||
// code. SB references in the code are encoded as ADRP pairs with zero
|
||||
|
||||
@@ -339,6 +339,16 @@ const (
|
||||
a64FEXTR // EXTR
|
||||
a64FBitfield // bitfield: BFI/BFXIL/SBFM/UBFM/BFM
|
||||
a64FSystem // system: NOP, BRK, etc.
|
||||
a64FFP3 // FP 3-operand (Rm, Rn, Rd): FADD, FSUB, FMUL, FDIV, etc.
|
||||
a64FFPUnary // FP unary (Rn, Rd): FMOV, FABS, FNEG, FSQRT, FCVT, FRINT*
|
||||
a64FFP4 // FP 4-operand FMA (Ra, Rm, Rn, Rd): FMADD, FMSUB, etc.
|
||||
a64FFPCmp // FP compare (Rm, Rn): FCMP, FCMPE
|
||||
a64FFPCCmp // FP conditional compare (Rm, Rn, nzcv, cond): FCCMP, FCCMPE
|
||||
a64FFPCvt // FP↔integer conversion: FCVTZS, SCVTF, etc.
|
||||
a64FFPSel // FP conditional select (Rm, Rn, Rd, cond): FCSEL
|
||||
a64FFMovGR // FMOV between GP and FP registers
|
||||
a64FCRC32 // CRC32
|
||||
a64FCSEL // conditional select: CSEL, CSINC, CSINV, CSNEG
|
||||
)
|
||||
|
||||
// a64Enc is one instruction's encoding: its bit layout (format) and the
|
||||
@@ -517,6 +527,141 @@ func init() {
|
||||
a64InstrTable["BFIW"] = a64Enc{format: a64FBitfield, op: 0<<31 | 2<<29 | 0x26<<23 | 0<<22}
|
||||
a64InstrTable["BFXIL"] = a64Enc{format: a64FBitfield, op: 1<<31 | 1<<29 | 0x26<<23 | 1<<22}
|
||||
a64InstrTable["BFXILW"] = a64Enc{format: a64FBitfield, op: 0<<31 | 1<<29 | 0x26<<23 | 0<<22}
|
||||
|
||||
// ---- FP 3-operand (Rm, Rn, Rd): FADD, FSUB, FMUL, FDIV, FMAX, FMIN, FNMUL ----
|
||||
fp3 := map[string]uint32{
|
||||
"FADDS": 0x1e202800, "FADDD": 0x1e602800,
|
||||
"FSUBS": 0x1e203800, "FSUBD": 0x1e603800,
|
||||
"FMULS": 0x1e200800, "FMULD": 0x1e600800,
|
||||
"FDIVS": 0x1e201800, "FDIVD": 0x1e601800,
|
||||
"FMAXS": 0x1e204800, "FMAXD": 0x1e604800,
|
||||
"FMINS": 0x1e205800, "FMIND": 0x1e605800,
|
||||
"FMAXNMS": 0x1e206800, "FMAXNMD": 0x1e606800,
|
||||
"FMINNMS": 0x1e207800, "FMINNMD": 0x1e607800,
|
||||
"FNMULS": 0x1e208800, "FNMULD": 0x1e608800,
|
||||
}
|
||||
for m, op := range fp3 {
|
||||
a64InstrTable[m] = a64Enc{format: a64FFP3, op: op}
|
||||
}
|
||||
|
||||
// ---- FP unary (Rn, Rd): FMOV reg-reg, FABS, FNEG, FSQRT, FCVT, FRINT* ----
|
||||
fp1 := map[string]uint32{
|
||||
"FMOVS": 0x1e204000, "FMOVD": 0x1e604000,
|
||||
"FABSS": 0x1e20c000, "FABSD": 0x1e60c000,
|
||||
"FNEGS": 0x1e214000, "FNEGD": 0x1e614000,
|
||||
"FSQRTS": 0x1e21c000, "FSQRTD": 0x1e61c000,
|
||||
"FCVTSD": 0x1e22c000, "FCVTDS": 0x1e624000,
|
||||
"FRINTNS": 0x1e244000, "FRINTND": 0x1e644000,
|
||||
"FRINTPS": 0x1e24c000, "FRINTPD": 0x1e64c000,
|
||||
"FRINTMS": 0x1e254000, "FRINTMD": 0x1e654000,
|
||||
"FRINTZS": 0x1e25c000, "FRINTZD": 0x1e65c000,
|
||||
"FRINTAS": 0x1e264000, "FRINTAD": 0x1e664000,
|
||||
"FRINTXS": 0x1e274000, "FRINTXD": 0x1e674000,
|
||||
"FRINTIS": 0x1e27c000, "FRINTID": 0x1e67c000,
|
||||
}
|
||||
for m, op := range fp1 {
|
||||
a64InstrTable[m] = a64Enc{format: a64FFPUnary, op: op}
|
||||
}
|
||||
|
||||
// ---- FP 4-operand FMA (Ra, Rm, Rn, Rd) ----
|
||||
fp4 := map[string]uint32{
|
||||
"FMADDS": 0x1f000000, "FMADDD": 0x1f400000,
|
||||
"FMSUBS": 0x1f008000, "FMSUBD": 0x1f408000,
|
||||
"FNMADDS": 0x1f200000, "FNMADDD": 0x1f600000,
|
||||
"FNMSUBS": 0x1f208000, "FNMSUBD": 0x1f608000,
|
||||
}
|
||||
for m, op := range fp4 {
|
||||
a64InstrTable[m] = a64Enc{format: a64FFP4, op: op}
|
||||
}
|
||||
|
||||
// ---- FP compare (Rm, Rn or #0, Rn) ----
|
||||
fpcmp := map[string]uint32{
|
||||
"FCMPS": 0x1e202000, "FCMPD": 0x1e602000,
|
||||
"FCMPES": 0x1e202010, "FCMPED": 0x1e602010,
|
||||
}
|
||||
for m, op := range fpcmp {
|
||||
a64InstrTable[m] = a64Enc{format: a64FFPCmp, op: op}
|
||||
}
|
||||
|
||||
// ---- FP conditional compare (Rm, Rn, #nzcv, cond) ----
|
||||
fpccmp := map[string]uint32{
|
||||
"FCCMPS": 0x1e200400, "FCCMPD": 0x1e600400,
|
||||
"FCCMPES": 0x1e200410, "FCCMPED": 0x1e600410,
|
||||
}
|
||||
for m, op := range fpccmp {
|
||||
a64InstrTable[m] = a64Enc{format: a64FFPCCmp, op: op}
|
||||
}
|
||||
|
||||
// ---- FP conditional select (Rm, Rn, Rd, cond) ----
|
||||
a64InstrTable["FCSELS"] = a64Enc{format: a64FFPSel, op: 0x1e200c00}
|
||||
a64InstrTable["FCSELD"] = a64Enc{format: a64FFPSel, op: 0x1e600c00}
|
||||
|
||||
// ---- FP ↔ integer conversion ----
|
||||
fpcvt := map[string]uint32{
|
||||
"FCVTZSD": 0x9e780000, "FCVTZSDW": 0x1e780000,
|
||||
"FCVTZSS": 0x9e380000, "FCVTZSSW": 0x1e380000,
|
||||
"FCVTZUD": 0x9e790000, "FCVTZUDW": 0x1e790000,
|
||||
"FCVTZUS": 0x9e390000, "FCVTZUSW": 0x1e390000,
|
||||
"SCVTFD": 0x9e620000, "SCVTFS": 0x9e220000,
|
||||
"SCVTFWD": 0x1e620000, "SCVTFWS": 0x1e220000,
|
||||
"UCVTFD": 0x9e630000, "UCVTFS": 0x9e230000,
|
||||
"UCVTFWD": 0x1e630000, "UCVTFWS": 0x1e230000,
|
||||
}
|
||||
for m, op := range fpcvt {
|
||||
a64InstrTable[m] = a64Enc{format: a64FFPCvt, op: op}
|
||||
}
|
||||
|
||||
// ---- FMOV between GP and FP registers ----
|
||||
a64InstrTable["FMOVGR"] = a64Enc{format: a64FFMovGR, op: 0x1e260000} // placeholder, actual encoding depends on direction
|
||||
|
||||
// ---- conditional select: CSEL, CSINC, CSINV, CSNEG ----
|
||||
csel := map[string]uint32{
|
||||
"CSEL": 0x9a800000, "CSELW": 0x1a800000,
|
||||
"CSINC": 0x9a800400, "CSINCW": 0x1a800400,
|
||||
"CSINV": 0xda800000, "CSINVW": 0x5a800000,
|
||||
"CSNEG": 0xda800400, "CSNEGW": 0x5a800400,
|
||||
}
|
||||
for m, op := range csel {
|
||||
a64InstrTable[m] = a64Enc{format: a64FCSEL, op: op}
|
||||
}
|
||||
// Aliases
|
||||
a64InstrTable["CSET"] = a64Enc{format: a64FCSEL, op: 0x9a800400}
|
||||
a64InstrTable["CSETW"] = a64Enc{format: a64FCSEL, op: 0x1a800400}
|
||||
a64InstrTable["CSETM"] = a64Enc{format: a64FCSEL, op: 0xda800000}
|
||||
a64InstrTable["CSETMW"] = a64Enc{format: a64FCSEL, op: 0x5a800000}
|
||||
a64InstrTable["CINC"] = a64Enc{format: a64FCSEL, op: 0x9a800400}
|
||||
a64InstrTable["CINCW"] = a64Enc{format: a64FCSEL, op: 0x1a800400}
|
||||
a64InstrTable["CINV"] = a64Enc{format: a64FCSEL, op: 0xda800000}
|
||||
a64InstrTable["CINVW"] = a64Enc{format: a64FCSEL, op: 0x5a800000}
|
||||
a64InstrTable["CNEG"] = a64Enc{format: a64FCSEL, op: 0xda800400}
|
||||
a64InstrTable["CNEGW"] = a64Enc{format: a64FCSEL, op: 0x5a800400}
|
||||
|
||||
// ---- CRC32 ----
|
||||
crc32 := map[string]uint32{
|
||||
"CRC32B": 0x1ac04000, "CRC32H": 0x1ac04400,
|
||||
"CRC32W": 0x1ac04800, "CRC32X": 0x9ac04c00,
|
||||
"CRC32CB": 0x1ac05000, "CRC32CH": 0x1ac05400,
|
||||
"CRC32CW": 0x1ac05800, "CRC32CX": 0x9ac05c00,
|
||||
}
|
||||
for m, op := range crc32 {
|
||||
a64InstrTable[m] = a64Enc{format: a64FCRC32, op: op}
|
||||
}
|
||||
|
||||
// ---- exclusive load/store ----
|
||||
// LDXR/STXR and variants
|
||||
a64InstrTable["LDXR"] = a64Enc{format: a64FLSU, op: 0xc85f7c00}
|
||||
a64InstrTable["LDXRB"] = a64Enc{format: a64FLSU, op: 0x085f7c00}
|
||||
a64InstrTable["LDXRH"] = a64Enc{format: a64FLSU, op: 0x485f7c00}
|
||||
a64InstrTable["LDXRW"] = a64Enc{format: a64FLSU, op: 0x885f7c00}
|
||||
a64InstrTable["LDAXR"] = a64Enc{format: a64FLSU, op: 0xc85ffc00}
|
||||
a64InstrTable["LDAXRB"] = a64Enc{format: a64FLSU, op: 0x085ffc00}
|
||||
a64InstrTable["LDAXRH"] = a64Enc{format: a64FLSU, op: 0x485ffc00}
|
||||
a64InstrTable["LDAXRW"] = a64Enc{format: a64FLSU, op: 0x885ffc00}
|
||||
|
||||
// ---- SIMD basics (VADD, VSUB, VMUL, VMOV) ----
|
||||
a64InstrTable["VADD"] = a64Enc{format: a64FFP3, op: 0x0e208400}
|
||||
a64InstrTable["VSUB"] = a64Enc{format: a64FFP3, op: 0x2e208400}
|
||||
a64InstrTable["VMUL"] = a64Enc{format: a64FFP3, op: 0x0e209c00}
|
||||
}
|
||||
|
||||
// ---- load/store helper tables ----
|
||||
|
||||
@@ -0,0 +1,142 @@
|
||||
// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
package asm
|
||||
|
||||
import (
|
||||
"bytes"
|
||||
"debug/elf"
|
||||
"testing"
|
||||
|
||||
"sourcedock.dev/petrbalvin/gasm-devkit/parser"
|
||||
)
|
||||
|
||||
// TestELFAARCH64Object checks the structure of the emitted AArch64 ELF64
|
||||
// relocatable object: sections, the symbol table (bindings, types, values,
|
||||
// sizes) and the .rela.text relocation pair for the static-symbol load,
|
||||
// parsed back with debug/elf.
|
||||
func TestELFAARCH64Object(t *testing.T) {
|
||||
f, errs := parser.Parse("k_arm64.s", `
|
||||
#include "textflag.h"
|
||||
|
||||
TEXT ·add(SB), NOSPLIT, $0-24
|
||||
MOVD a+0(FP), R4
|
||||
MOVD b+8(FP), R5
|
||||
ADD R5, R4, R4
|
||||
MOVD R4, ret+16(FP)
|
||||
RET
|
||||
|
||||
TEXT ·getanswer(SB), NOSPLIT, $0-8
|
||||
MOVD answer<>(SB), R4
|
||||
MOVD R4, ret+0(FP)
|
||||
RET
|
||||
|
||||
GLOBL answer<>(SB), RODATA, $8
|
||||
DATA answer<>+0(SB)/8, $42
|
||||
`)
|
||||
if len(errs) > 0 {
|
||||
t.Fatalf("parse: %v", errs)
|
||||
}
|
||||
img, err := AssembleFileARM64(f)
|
||||
if err != nil {
|
||||
t.Fatalf("AssembleFileARM64: %v", err)
|
||||
}
|
||||
obj, err := img.ELFAARCH64Object()
|
||||
if err != nil {
|
||||
t.Fatalf("ELFAARCH64Object: %v", err)
|
||||
}
|
||||
ef, err := elf.NewFile(bytes.NewReader(obj))
|
||||
if err != nil {
|
||||
t.Fatalf("parse emitted object: %v", err)
|
||||
}
|
||||
defer ef.Close()
|
||||
|
||||
if ef.Type != elf.ET_REL || ef.Machine != elf.EM_AARCH64 {
|
||||
t.Errorf("type/machine = %v/%v, want ET_REL/EM_AARCH64", ef.Type, ef.Machine)
|
||||
}
|
||||
|
||||
text := ef.Section(".text")
|
||||
data := ef.Section(".data")
|
||||
if text == nil || data == nil {
|
||||
t.Fatal("missing .text or .data section")
|
||||
}
|
||||
if text.Size == 0 {
|
||||
t.Error(".text section is empty")
|
||||
}
|
||||
|
||||
syms, err := ef.Symbols()
|
||||
if err != nil {
|
||||
t.Fatalf("symbols: %v", err)
|
||||
}
|
||||
|
||||
foundAdd, foundGetanswer, foundAnswer := false, false, false
|
||||
for _, s := range syms {
|
||||
switch s.Name {
|
||||
case "add":
|
||||
foundAdd = true
|
||||
if elf.SymType(s.Info&0xf) != elf.STT_FUNC || elf.SymBind(s.Info>>4) != elf.STB_GLOBAL {
|
||||
t.Errorf("add: info=0x%02x, want STT_FUNC|STB_GLOBAL", s.Info)
|
||||
}
|
||||
case "getanswer":
|
||||
foundGetanswer = true
|
||||
if elf.SymType(s.Info&0xf) != elf.STT_FUNC || elf.SymBind(s.Info>>4) != elf.STB_GLOBAL {
|
||||
t.Errorf("getanswer: info=0x%02x, want STT_FUNC|STB_GLOBAL", s.Info)
|
||||
}
|
||||
case "answer":
|
||||
foundAnswer = true
|
||||
if elf.SymType(s.Info&0xf) != elf.STT_OBJECT || elf.SymBind(s.Info>>4) != elf.STB_LOCAL {
|
||||
t.Errorf("answer: info=0x%02x, want STT_OBJECT|STB_LOCAL", s.Info)
|
||||
}
|
||||
}
|
||||
}
|
||||
if !foundAdd {
|
||||
t.Error("symbol 'add' not found")
|
||||
}
|
||||
if !foundGetanswer {
|
||||
t.Error("symbol 'getanswer' not found")
|
||||
}
|
||||
if !foundAnswer {
|
||||
t.Error("symbol 'answer' not found")
|
||||
}
|
||||
|
||||
// Check that .rela.text exists (getanswer has SB reference).
|
||||
relaText := ef.Section(".rela.text")
|
||||
if relaText == nil {
|
||||
t.Error("missing .rela.text section")
|
||||
}
|
||||
}
|
||||
|
||||
// TestELFAARCH64ObjectNoRelocations checks the ELF output when there are no
|
||||
// static-symbol references (no .rela.text section).
|
||||
func TestELFAARCH64ObjectNoRelocations(t *testing.T) {
|
||||
f, errs := parser.Parse("k_arm64.s", `
|
||||
#include "textflag.h"
|
||||
|
||||
TEXT ·add(SB), NOSPLIT, $0-24
|
||||
MOVD a+0(FP), R4
|
||||
MOVD b+8(FP), R5
|
||||
ADD R5, R4, R4
|
||||
MOVD R4, ret+16(FP)
|
||||
RET
|
||||
`)
|
||||
if len(errs) > 0 {
|
||||
t.Fatalf("parse: %v", errs)
|
||||
}
|
||||
img, err := AssembleFileARM64(f)
|
||||
if err != nil {
|
||||
t.Fatalf("AssembleFileARM64: %v", err)
|
||||
}
|
||||
obj, err := img.ELFAARCH64Object()
|
||||
if err != nil {
|
||||
t.Fatalf("ELFAARCH64Object: %v", err)
|
||||
}
|
||||
ef, err := elf.NewFile(bytes.NewReader(obj))
|
||||
if err != nil {
|
||||
t.Fatalf("parse emitted object: %v", err)
|
||||
}
|
||||
defer ef.Close()
|
||||
|
||||
if ef.Section(".rela.text") != nil {
|
||||
t.Error("unexpected .rela.text section when there are no relocations")
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user