feat(asm): encode the arm64 SVE2 crypto, counter and reduction families
Assisted-by: GLM 5.3
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@@ -316,7 +316,11 @@ func TestArm64ExtTableIntegrity(t *testing.T) {
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}
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roundOne := in.Form == ExtFormVectors || in.Form == ExtFormPredicated ||
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in.Form == ExtFormImmediate || in.Form == ExtFormSignedImmediate
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if in.Word&destMask != 0 || (roundOne && in.Size.Width != 0 && in.Word&(0x3<<22) != 0) {
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// The loop terminators carry no destination at all, and the NE
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// variants put their opcode right in the slot another class would
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// fill with one, so the zero-destination invariant exempts them.
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term := in.Form == ExtFormCTerm
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if !term && (in.Word&destMask != 0 || (roundOne && in.Size.Width != 0 && in.Word&(0x3<<22) != 0)) {
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t.Errorf("%s: word %08x carries destination or size bits, want them zero", in.Name, in.Word)
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}
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}
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@@ -1068,3 +1072,253 @@ func TestArm64ExtZGolden(t *testing.T) {
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}
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}
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}
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// TestArm64ExtStage3Golden pins the stage-three families, the SVE2 crypto
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// group (the multi-precision carry steps, the SHA3 rotate, SM4 and AES), the
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// predicate counters and loop terminators (CNTP, the DECP and INCP steps,
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// the saturating variants and CTERM), the 32-bit while compares, and the SVE
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// reductions into a SIMD register (ANDV, EORV, ORV, SADDV, UADDV, the maxima
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// and minima, the floating-point sums and FADDA). Every row is one
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// arm64sveenc.s line and the want word is that line's own encoding, the
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// same provenance as the families above: the toolchain encoding table and
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// its generated corpus, both produced from Arm's official ISA description.
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func TestArm64ExtStage3Golden(t *testing.T) {
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for _, tt := range []struct {
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name string
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mnem string
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form ExtForm
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arr ExtArrangement
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ops []ExtOperand
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want uint32
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}{
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// The crypto family: Zm, Zn, Zd over a locked arrangement.
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{"ZADCLB Z7.D, Z23.D, Z13.D", "ZADCLB", ExtFormVectorsZm, ExtArrD,
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[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(23, ExtArrD), ExtVector(13, ExtArrD)},
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0x4547d2ed},
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{"ZADCLT Z7.D, Z23.D, Z13.D", "ZADCLT", ExtFormVectorsZm, ExtArrD,
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[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(23, ExtArrD), ExtVector(13, ExtArrD)},
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0x4547d6ed},
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{"ZSBCLB Z7.D, Z23.D, Z13.D", "ZSBCLB", ExtFormVectorsZm, ExtArrD,
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[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(23, ExtArrD), ExtVector(13, ExtArrD)},
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0x45c7d2ed},
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{"ZSBCLT Z7.D, Z23.D, Z13.D", "ZSBCLT", ExtFormVectorsZm, ExtArrD,
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[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(23, ExtArrD), ExtVector(13, ExtArrD)},
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0x45c7d6ed},
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{"ZRAX1 Z7.D, Z6.D, Z23.D", "ZRAX1", ExtFormVectorsZm, ExtArrD,
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[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(6, ExtArrD), ExtVector(23, ExtArrD)},
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0x4527f4d7},
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{"ZSM4EKEY Z7.S, Z6.S, Z23.S", "ZSM4EKEY", ExtFormVectorsZm, ExtArrS,
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[]ExtOperand{ExtVector(7, ExtArrS), ExtVector(6, ExtArrS), ExtVector(23, ExtArrS)},
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0x4527f0d7},
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{"ZSM4E Z7.S, Z6.S, Z6.S", "ZSM4E", ExtFormZReadBack, ExtArrS,
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[]ExtOperand{ExtVector(7, ExtArrS), ExtVector(6, ExtArrS), ExtVector(6, ExtArrS)},
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0x4523e0e6},
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{"ZAESD Z7.B, Z6.B, Z6.B", "ZAESD", ExtFormZReadBack, ExtArrB,
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[]ExtOperand{ExtVector(7, ExtArrB), ExtVector(6, ExtArrB), ExtVector(6, ExtArrB)},
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0x4522e4e6},
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{"ZAESE Z7.B, Z6.B, Z6.B", "ZAESE", ExtFormZReadBack, ExtArrB,
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[]ExtOperand{ExtVector(7, ExtArrB), ExtVector(6, ExtArrB), ExtVector(6, ExtArrB)},
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0x4522e0e6},
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{"ZAESIMC Z11.B, Z11.B", "ZAESIMC", ExtFormZSameReg, ExtArrB,
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[]ExtOperand{ExtVector(11, ExtArrB), ExtVector(11, ExtArrB)},
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0x4520e40b},
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{"ZAESMC Z11.B, Z11.B", "ZAESMC", ExtFormZSameReg, ExtArrB,
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[]ExtOperand{ExtVector(11, ExtArrB), ExtVector(11, ExtArrB)},
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0x4520e00b},
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// The terminators and counters.
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{"CTERMEQ ZR, R25", "CTERMEQ", ExtFormCTerm, ExtArrNone,
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[]ExtOperand{ExtZeroRegister(), ExtGeneral(25)},
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0x25ff2320},
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{"CTERMEQW ZR, R25", "CTERMEQW", ExtFormCTerm, ExtArrNone,
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[]ExtOperand{ExtZeroRegister(), ExtGeneral(25)},
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0x25bf2320},
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{"CTERMNE ZR, R25", "CTERMNE", ExtFormCTerm, ExtArrNone,
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[]ExtOperand{ExtZeroRegister(), ExtGeneral(25)},
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0x25ff2330},
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{"CTERMNEW ZR, R25", "CTERMNEW", ExtFormCTerm, ExtArrNone,
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[]ExtOperand{ExtZeroRegister(), ExtGeneral(25)},
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0x25bf2330},
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{"PCNTP P2.B, P14, R2", "PCNTP", ExtFormCountP, ExtArrNone,
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[]ExtOperand{ExtPredicateSized(2, ExtArrB), ExtPredicateSized(14, ExtArrNone), ExtGeneral(2)},
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0x2520b842},
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{"PFIRSTP P2.B, P14, R2", "PFIRSTP", ExtFormCountP, ExtArrNone,
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[]ExtOperand{ExtPredicateSized(2, ExtArrB), ExtPredicateSized(14, ExtArrNone), ExtGeneral(2)},
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0x2521b842},
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{"PLASTP P2.B, P14, R2", "PLASTP", ExtFormCountP, ExtArrNone,
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[]ExtOperand{ExtPredicateSized(2, ExtArrB), ExtPredicateSized(14, ExtArrNone), ExtGeneral(2)},
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0x2522b842},
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{"PDECP P14.S, ZR", "PDECP", ExtFormCountPn, ExtArrNone,
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[]ExtOperand{ExtPredicateSized(14, ExtArrS), ExtZeroRegister()},
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0x25ad89df},
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{"PINCP P14.S, ZR", "PINCP", ExtFormCountPn, ExtArrNone,
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[]ExtOperand{ExtPredicateSized(14, ExtArrS), ExtZeroRegister()},
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0x25ac89df},
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{"PSQDECP P14.S, ZR", "PSQDECP", ExtFormCountPn, ExtArrNone,
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[]ExtOperand{ExtPredicateSized(14, ExtArrS), ExtZeroRegister()},
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0x25aa8ddf},
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{"PSQINCP P14.S, ZR", "PSQINCP", ExtFormCountPn, ExtArrNone,
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[]ExtOperand{ExtPredicateSized(14, ExtArrS), ExtZeroRegister()},
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0x25a88ddf},
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{"PUQDECP P14.S, ZR", "PUQDECP", ExtFormCountPn, ExtArrNone,
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[]ExtOperand{ExtPredicateSized(14, ExtArrS), ExtZeroRegister()},
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0x25ab8ddf},
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{"PUQINCP P14.S, ZR", "PUQINCP", ExtFormCountPn, ExtArrNone,
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[]ExtOperand{ExtPredicateSized(14, ExtArrS), ExtZeroRegister()},
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0x25a98ddf},
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{"PUQDECPW P14.S, ZR", "PUQDECPW", ExtFormCountPn, ExtArrNone,
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[]ExtOperand{ExtPredicateSized(14, ExtArrS), ExtZeroRegister()},
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0x25ab89df},
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{"PUQINCPW P14.S, ZR", "PUQINCPW", ExtFormCountPn, ExtArrNone,
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[]ExtOperand{ExtPredicateSized(14, ExtArrS), ExtZeroRegister()},
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0x25a989df},
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{"PSQDECPW R8, P10.D, R8", "PSQDECPW", ExtFormCountPnW, ExtArrNone,
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[]ExtOperand{ExtGeneral(8), ExtPredicateSized(10, ExtArrD), ExtGeneral(8)},
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0x25ea8948},
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{"PSQINCPW R8, P10.D, R8", "PSQINCPW", ExtFormCountPnW, ExtArrNone,
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[]ExtOperand{ExtGeneral(8), ExtPredicateSized(10, ExtArrD), ExtGeneral(8)},
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0x25e88948},
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{"PWHILEGEW R2, R10, P10.H", "PWHILEGEW", ExtFormWhile, ExtArrNone,
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[]ExtOperand{ExtGeneral(2), ExtGeneral(10), ExtPredicateSized(10, ExtArrH)},
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0x2562014a},
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{"PWHILEGTW R2, R10, P10.H", "PWHILEGTW", ExtFormWhile, ExtArrNone,
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[]ExtOperand{ExtGeneral(2), ExtGeneral(10), ExtPredicateSized(10, ExtArrH)},
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0x2562015a},
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{"PWHILEHIW R2, R10, P10.H", "PWHILEHIW", ExtFormWhile, ExtArrNone,
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[]ExtOperand{ExtGeneral(2), ExtGeneral(10), ExtPredicateSized(10, ExtArrH)},
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0x2562095a},
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{"PWHILEHSW R2, R10, P10.H", "PWHILEHSW", ExtFormWhile, ExtArrNone,
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[]ExtOperand{ExtGeneral(2), ExtGeneral(10), ExtPredicateSized(10, ExtArrH)},
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0x2562094a},
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{"PWHILELEW R2, R10, P10.H", "PWHILELEW", ExtFormWhile, ExtArrNone,
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[]ExtOperand{ExtGeneral(2), ExtGeneral(10), ExtPredicateSized(10, ExtArrH)},
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0x2562055a},
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{"PWHILELOW R2, R10, P10.H", "PWHILELOW", ExtFormWhile, ExtArrNone,
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[]ExtOperand{ExtGeneral(2), ExtGeneral(10), ExtPredicateSized(10, ExtArrH)},
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0x25620d4a},
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{"PWHILELSW R2, R10, P10.H", "PWHILELSW", ExtFormWhile, ExtArrNone,
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[]ExtOperand{ExtGeneral(2), ExtGeneral(10), ExtPredicateSized(10, ExtArrH)},
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0x25620d5a},
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{"PWHILELTW R2, R10, P10.H", "PWHILELTW", ExtFormWhile, ExtArrNone,
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[]ExtOperand{ExtGeneral(2), ExtGeneral(10), ExtPredicateSized(10, ExtArrH)},
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0x2562054a},
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// The reductions.
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{"ZSADDVD Z6.B, P3, V2", "ZSADDVD", ExtFormReduce, ExtArrNone,
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[]ExtOperand{ExtVector(6, ExtArrB), ExtPredicateSized(3, ExtArrNone), ExtSIMD(2)},
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0x04002cc2},
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{"ZSADDVD Z6.D, P3, V2", "ZSADDVD", ExtFormReduce, ExtArrNone,
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[]ExtOperand{ExtVector(6, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(2)},
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0x04c02cc2},
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{"ZUADDVD Z10.D, P3, V15", "ZUADDVD", ExtFormReduce, ExtArrNone,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x04c12d4f},
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{"ZUADDVD Z10.B, P3, V15", "ZUADDVD", ExtFormReduce, ExtArrNone,
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[]ExtOperand{ExtVector(10, ExtArrB), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x04012d4f},
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{"ZANDVB Z6.B, P3, V2", "ZANDVB", ExtFormReduce, ExtArrB,
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[]ExtOperand{ExtVector(6, ExtArrB), ExtPredicateSized(3, ExtArrNone), ExtSIMD(2)},
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0x041a2cc2},
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{"ZANDVH Z3.H, P1, V29", "ZANDVH", ExtFormReduce, ExtArrH,
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[]ExtOperand{ExtVector(3, ExtArrH), ExtPredicateSized(1, ExtArrNone), ExtSIMD(29)},
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0x045a247d},
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{"ZANDVS Z17.S, P1, V27", "ZANDVS", ExtFormReduce, ExtArrS,
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[]ExtOperand{ExtVector(17, ExtArrS), ExtPredicateSized(1, ExtArrNone), ExtSIMD(27)},
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0x049a263b},
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{"ZANDVD Z10.D, P3, V15", "ZANDVD", ExtFormReduce, ExtArrD,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x04da2d4f},
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{"ZEORVB Z6.B, P3, V2", "ZEORVB", ExtFormReduce, ExtArrB,
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[]ExtOperand{ExtVector(6, ExtArrB), ExtPredicateSized(3, ExtArrNone), ExtSIMD(2)},
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0x04192cc2},
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{"ZEORVD Z10.D, P3, V15", "ZEORVD", ExtFormReduce, ExtArrD,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x04d92d4f},
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{"ZORVB Z6.B, P3, V2", "ZORVB", ExtFormReduce, ExtArrB,
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[]ExtOperand{ExtVector(6, ExtArrB), ExtPredicateSized(3, ExtArrNone), ExtSIMD(2)},
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0x04182cc2},
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{"ZORVD Z10.D, P3, V15", "ZORVD", ExtFormReduce, ExtArrD,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x04d82d4f},
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{"ZSMAXVB Z6.B, P3, V2", "ZSMAXVB", ExtFormReduce, ExtArrB,
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[]ExtOperand{ExtVector(6, ExtArrB), ExtPredicateSized(3, ExtArrNone), ExtSIMD(2)},
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0x04082cc2},
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{"ZSMAXVH Z3.H, P1, V29", "ZSMAXVH", ExtFormReduce, ExtArrH,
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[]ExtOperand{ExtVector(3, ExtArrH), ExtPredicateSized(1, ExtArrNone), ExtSIMD(29)},
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0x0448247d},
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{"ZSMAXVS Z17.S, P1, V27", "ZSMAXVS", ExtFormReduce, ExtArrS,
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[]ExtOperand{ExtVector(17, ExtArrS), ExtPredicateSized(1, ExtArrNone), ExtSIMD(27)},
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0x0488263b},
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{"ZSMAXVD Z10.D, P3, V15", "ZSMAXVD", ExtFormReduce, ExtArrD,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x04c82d4f},
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{"ZSMINVB Z6.B, P3, V2", "ZSMINVB", ExtFormReduce, ExtArrB,
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[]ExtOperand{ExtVector(6, ExtArrB), ExtPredicateSized(3, ExtArrNone), ExtSIMD(2)},
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0x040a2cc2},
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{"ZSMINVD Z10.D, P3, V15", "ZSMINVD", ExtFormReduce, ExtArrD,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x04ca2d4f},
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{"ZUMAXVB Z6.B, P3, V2", "ZUMAXVB", ExtFormReduce, ExtArrB,
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[]ExtOperand{ExtVector(6, ExtArrB), ExtPredicateSized(3, ExtArrNone), ExtSIMD(2)},
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0x04092cc2},
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{"ZUMAXVD Z10.D, P3, V15", "ZUMAXVD", ExtFormReduce, ExtArrD,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x04c92d4f},
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{"ZUMINVB Z6.B, P3, V2", "ZUMINVB", ExtFormReduce, ExtArrB,
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[]ExtOperand{ExtVector(6, ExtArrB), ExtPredicateSized(3, ExtArrNone), ExtSIMD(2)},
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0x040b2cc2},
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{"ZUMINVD Z10.D, P3, V15", "ZUMINVD", ExtFormReduce, ExtArrD,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x04cb2d4f},
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{"ZFADDVH Z3.H, P1, V29", "ZFADDVH", ExtFormReduce, ExtArrH,
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[]ExtOperand{ExtVector(3, ExtArrH), ExtPredicateSized(1, ExtArrNone), ExtSIMD(29)},
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0x6540247d},
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{"ZFADDVS Z17.S, P1, V27", "ZFADDVS", ExtFormReduce, ExtArrS,
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[]ExtOperand{ExtVector(17, ExtArrS), ExtPredicateSized(1, ExtArrNone), ExtSIMD(27)},
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0x6580263b},
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{"ZFADDVD Z10.D, P3, V15", "ZFADDVD", ExtFormReduce, ExtArrD,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x65c02d4f},
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{"ZFMAXNMVH Z3.H, P1, V29", "ZFMAXNMVH", ExtFormReduce, ExtArrH,
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[]ExtOperand{ExtVector(3, ExtArrH), ExtPredicateSized(1, ExtArrNone), ExtSIMD(29)},
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0x6544247d},
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{"ZFMAXNMVD Z10.D, P3, V15", "ZFMAXNMVD", ExtFormReduce, ExtArrD,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x65c42d4f},
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{"ZFMAXVH Z3.H, P1, V29", "ZFMAXVH", ExtFormReduce, ExtArrH,
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[]ExtOperand{ExtVector(3, ExtArrH), ExtPredicateSized(1, ExtArrNone), ExtSIMD(29)},
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0x6546247d},
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{"ZFMAXVD Z10.D, P3, V15", "ZFMAXVD", ExtFormReduce, ExtArrD,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x65c62d4f},
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{"ZFMINNMVH Z3.H, P1, V29", "ZFMINNMVH", ExtFormReduce, ExtArrH,
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[]ExtOperand{ExtVector(3, ExtArrH), ExtPredicateSized(1, ExtArrNone), ExtSIMD(29)},
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0x6545247d},
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{"ZFMINNMVD Z10.D, P3, V15", "ZFMINNMVD", ExtFormReduce, ExtArrD,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x65c52d4f},
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{"ZFMINVH Z3.H, P1, V29", "ZFMINVH", ExtFormReduce, ExtArrH,
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[]ExtOperand{ExtVector(3, ExtArrH), ExtPredicateSized(1, ExtArrNone), ExtSIMD(29)},
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0x6547247d},
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{"ZFMINVD Z10.D, P3, V15", "ZFMINVD", ExtFormReduce, ExtArrD,
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[]ExtOperand{ExtVector(10, ExtArrD), ExtPredicateSized(3, ExtArrNone), ExtSIMD(15)},
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0x65c72d4f},
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{"ZFADDAH Z8.H, V15, P2, V15", "ZFADDAH", ExtFormReduceReadBack, ExtArrH,
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[]ExtOperand{ExtVector(8, ExtArrH), ExtSIMD(15), ExtPredicateSized(2, ExtArrNone), ExtSIMD(15)},
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0x6558290f},
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{"ZFADDAS Z26.S, V30, P7, V30", "ZFADDAS", ExtFormReduceReadBack, ExtArrS,
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[]ExtOperand{ExtVector(26, ExtArrS), ExtSIMD(30), ExtPredicateSized(7, ExtArrNone), ExtSIMD(30)},
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0x65983f5e},
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{"ZFADDAD Z9.D, V10, P2, V10", "ZFADDAD", ExtFormReduceReadBack, ExtArrD,
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[]ExtOperand{ExtVector(9, ExtArrD), ExtSIMD(10), ExtPredicateSized(2, ExtArrNone), ExtSIMD(10)},
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0x65d8292a},
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} {
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in := extInstructionMeta(t, tt.mnem, tt.form, ExtQualNone, tt.arr)
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got, err := in.Encode(tt.ops)
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if err != nil {
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t.Errorf("%s: encode: %v", tt.name, err)
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continue
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}
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if want := hex.EncodeToString(extWordLE(tt.want)); hex.EncodeToString(got) != want {
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t.Errorf("%s:\n got %x\n want %s", tt.name, got, want)
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}
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}
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}
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