feat(asm): encode the arm64 SVE2 crypto, counter and reduction families
Assisted-by: GLM 5.3
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@@ -424,3 +424,141 @@ func TestArm64AssembleExtensionStage2Golden(t *testing.T) {
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}
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}
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}
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// TestArm64AssembleExtensionStage3Golden drives the stage-three families
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// through the full assembler: corpus text in, corpus word out. The
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// statements carry the spellings the layer reads: the read-back crypto
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// destinations, the ZR of the dropped counter results, the bare governing
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// predicates and the V destinations of the reductions.
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func TestArm64AssembleExtensionStage3Golden(t *testing.T) {
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tests := []struct {
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stmt string
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want uint32
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}{
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// The crypto family.
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{"ZADCLB Z7.D, Z23.D, Z13.D", 0x4547d2ed},
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{"ZADCLT Z7.D, Z23.D, Z13.D", 0x4547d6ed},
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{"ZSBCLB Z7.D, Z23.D, Z13.D", 0x45c7d2ed},
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{"ZSBCLT Z7.D, Z23.D, Z13.D", 0x45c7d6ed},
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{"ZRAX1 Z7.D, Z6.D, Z23.D", 0x4527f4d7},
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{"ZSM4EKEY Z7.S, Z6.S, Z23.S", 0x4527f0d7},
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{"ZSM4E Z7.S, Z6.S, Z6.S", 0x4523e0e6},
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{"ZAESD Z7.B, Z6.B, Z6.B", 0x4522e4e6},
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{"ZAESE Z7.B, Z6.B, Z6.B", 0x4522e0e6},
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{"ZAESIMC Z11.B, Z11.B", 0x4520e40b},
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{"ZAESMC Z11.B, Z11.B", 0x4520e00b},
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// The terminators and counters.
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{"CTERMEQ ZR, R25", 0x25ff2320},
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{"CTERMEQW ZR, R25", 0x25bf2320},
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{"CTERMNE ZR, R25", 0x25ff2330},
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{"CTERMNEW ZR, R25", 0x25bf2330},
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{"CTERMEQ R0, R25", 0x25e02320},
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{"PCNTP P2.B, P14, R2", 0x2520b842},
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{"PFIRSTP P2.B, P14, R2", 0x2521b842},
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{"PLASTP P2.B, P14, R2", 0x2522b842},
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{"PDECP P14.S, ZR", 0x25ad89df},
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{"PINCP P14.S, ZR", 0x25ac89df},
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{"PSQDECP P14.S, ZR", 0x25aa8ddf},
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{"PSQINCP P14.S, ZR", 0x25a88ddf},
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{"PUQDECP P14.S, ZR", 0x25ab8ddf},
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{"PUQINCP P14.S, ZR", 0x25a98ddf},
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{"PUQDECPW P14.S, ZR", 0x25ab89df},
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{"PUQINCPW P14.S, ZR", 0x25a989df},
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{"PSQDECPW R8, P10.D, R8", 0x25ea8948},
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{"PSQINCPW R8, P10.D, R8", 0x25e88948},
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{"PWHILEGEW R2, R10, P10.H", 0x2562014a},
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{"PWHILEGTW R2, R10, P10.H", 0x2562015a},
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{"PWHILEHIW R2, R10, P10.H", 0x2562095a},
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{"PWHILEHSW R2, R10, P10.H", 0x2562094a},
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{"PWHILELEW R2, R10, P10.H", 0x2562055a},
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{"PWHILELOW R2, R10, P10.H", 0x25620d4a},
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{"PWHILELSW R2, R10, P10.H", 0x25620d5a},
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{"PWHILELTW R2, R10, P10.H", 0x2562054a},
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// The reductions.
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{"ZSADDVD Z6.B, P3, V2", 0x04002cc2},
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{"ZUADDVD Z10.D, P3, V15", 0x04c12d4f},
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{"ZANDVB Z6.B, P3, V2", 0x041a2cc2},
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{"ZANDVH Z3.H, P1, V29", 0x045a247d},
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{"ZANDVS Z17.S, P1, V27", 0x049a263b},
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{"ZANDVD Z10.D, P3, V15", 0x04da2d4f},
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{"ZEORVB Z6.B, P3, V2", 0x04192cc2},
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{"ZEORVD Z10.D, P3, V15", 0x04d92d4f},
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{"ZORVB Z6.B, P3, V2", 0x04182cc2},
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{"ZORVD Z10.D, P3, V15", 0x04d82d4f},
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{"ZSMAXVB Z6.B, P3, V2", 0x04082cc2},
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{"ZSMAXVH Z3.H, P1, V29", 0x0448247d},
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{"ZSMAXVS Z17.S, P1, V27", 0x0488263b},
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{"ZSMAXVD Z10.D, P3, V15", 0x04c82d4f},
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{"ZSMINVB Z6.B, P3, V2", 0x040a2cc2},
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{"ZSMINVD Z10.D, P3, V15", 0x04ca2d4f},
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{"ZUMAXVB Z6.B, P3, V2", 0x04092cc2},
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{"ZUMAXVD Z10.D, P3, V15", 0x04c92d4f},
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{"ZUMINVB Z6.B, P3, V2", 0x040b2cc2},
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{"ZUMINVD Z10.D, P3, V15", 0x04cb2d4f},
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{"ZFADDVH Z3.H, P1, V29", 0x6540247d},
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{"ZFADDVS Z17.S, P1, V27", 0x6580263b},
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{"ZFADDVD Z10.D, P3, V15", 0x65c02d4f},
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{"ZFMAXNMVH Z3.H, P1, V29", 0x6544247d},
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{"ZFMAXNMVD Z10.D, P3, V15", 0x65c42d4f},
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{"ZFMAXVH Z3.H, P1, V29", 0x6546247d},
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{"ZFMAXVD Z10.D, P3, V15", 0x65c62d4f},
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{"ZFMINNMVH Z3.H, P1, V29", 0x6545247d},
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{"ZFMINNMVD Z10.D, P3, V15", 0x65c52d4f},
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{"ZFMINVH Z3.H, P1, V29", 0x6547247d},
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{"ZFMINVD Z10.D, P3, V15", 0x65c72d4f},
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{"ZFADDAH Z8.H, V15, P2, V15", 0x6558290f},
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{"ZFADDAS Z26.S, V30, P7, V30", 0x65983f5e},
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{"ZFADDAD Z9.D, V10, P2, V10", 0x65d8292a},
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}
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for _, tt := range tests {
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words := assembleArm64Words(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")
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if len(words) != 2 {
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t.Fatalf("%s: got %d words, want the statement and RET", tt.stmt, len(words))
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}
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if words[0] != tt.want {
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t.Errorf("%s:\n got %08x\n want %08x", tt.stmt, words[0], tt.want)
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}
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if words[1] != 0xd65f03c0 {
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t.Errorf("%s: RET encoded %08x", tt.stmt, words[1])
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}
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}
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}
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// TestArm64AssembleExtensionStage3Refusals pins the diagnostics the
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// stage-three statements get from the layer: the read-back mismatches, the
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// locked arrangements, the dropped-result zero register and the narrow
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// governing predicates.
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func TestArm64AssembleExtensionStage3Refusals(t *testing.T) {
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tests := []struct {
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stmt string
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want string
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}{
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{"ZSM4E Z7.S, Z6.S, Z5.S", "the same register Zd"},
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{"ZSM4E Z7.D, Z6.D, Z6.D", "want .S"},
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{"ZAESIMC Z11.B, Z12.B", "the same register Zd"},
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{"ZADCLB Z7.S, Z23.S, Z13.S", "want .D"},
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{"CTERMEQ RSP, R25", "wants ZR here"},
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{"CTERMEQ R31, R25", "outside R0-R30"},
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{"PCNTP P2.B, P14, R31", "outside R0-R30"},
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{"PCNTP P2.Q, P14, R2", "no size encoding"},
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{"PDECP P14.S, R0", "spelled ZR"},
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{"PDECP P14.Q, ZR", "no size encoding"},
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{"PSQDECPW R8, P10.D, R9", "the same register"},
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{"ZSADDVD Z6.B, P9, V2", "outside P0-P7"},
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{"ZSADDVD Z6.B, P3/M, V2", "takes no qualifier"},
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{"ZSADDVD Z6.B, P3, V32", "outside V0-V31"},
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{"ZSADDVD Z6.B, P3, R2", "wants a SIMD register"},
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{"ZANDVB Z6.S, P3, V2", "want .B"},
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{"ZFADDAD Z9.D, V10, P2, V11", "the same register Vd"},
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{"PWHILEGEW R2, R10, P10.H", ""},
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}
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for _, tt := range tests {
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if tt.want == "" {
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continue
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}
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got := assembleArm64SrcError(t, arm64ExtProbeHead+"\t"+tt.stmt+"\n\tRET\n")
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if !strings.Contains(got, tt.want) {
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t.Errorf("%s: error %q does not name %q", tt.stmt, got, tt.want)
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}
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}
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}
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