feat(amd64): encode the GOROOT instruction families

Assisted-by: DeepSeek V4.1 Flash

asm/vex_test.go

@@ -19,6 +19,20 @@ func vreg(t *testing.T, name string) Reg {
 	return r
 }
 
+// x86asmUnrecognised lists the VEX mnemonics whose machine code the
+// golang.org/x/arch decoder cannot resolve; their bytes are verified against
+// go tool asm in the ground-truth tests instead.
+var x86asmUnrecognised = map[string]bool{
+	"ANDNL":        true,
+	"ANDNQ":        true,
+	"MULXL":        true,
+	"MULXQ":        true,
+	"RORXL":        true,
+	"RORXQ":        true,
+	"VFMADD213SD":  true,
+	"VFNMADD231SD": true,
+}
+
 // TestVexNDS3 encodes `mnem Y0, Y1, Y2` for every three-operand NDS
 // instruction and verifies it round-trips through the x86 decoder to the same
 // mnemonic.  A wrong opcode/map/pp surfaces as a different decoded instruction.
@@ -37,8 +51,15 @@ func TestVexNDS3(t *testing.T) {
 			t.Errorf("%s: Encode: %v", mnem, err)
 			continue
 		}
+		// The x86 decoder's table lacks a handful of rows the Go assembler
+		// emits (the scalar 213/231 FMA spellings among them); those are
+		// pinned byte for byte against go tool asm in TestVexGroundTruth
+		// instead of round-tripped here.
 		inst, err := x86asm.Decode(code, 64)
 		if err != nil {
+			if strings.Contains(err.Error(), "unrecognized instruction") && x86asmUnrecognised[mnem] {
+				continue
+			}
 			t.Errorf("%s: Decode(% x): %v", mnem, err, code)
 			continue
 		}
@@ -184,6 +205,38 @@ func TestVexGroundTruth(t *testing.T) {
 		{"VMULSD X0,X1,X1", "VMULSD", []Operand{vreg(t, "X0"), vreg(t, "X1"), vreg(t, "X1")}, "c5f359c8", ""},
 		{"VFMADD231PD Y14,Y12,Y8", "VFMADD231PD", []Operand{vreg(t, "Y14"), vreg(t, "Y12"), vreg(t, "Y8")}, "c4429db8c6", ""},
 		{"VFMADD231PD (DI),Y12,Y8", "VFMADD231PD", []Operand{Ptr(DI, 0, 32), vreg(t, "Y12"), vreg(t, "Y8")}, "c4629db807", ""},
+		{"VFMADD213SD X0,X1,X2", "VFMADD213SD", []Operand{vreg(t, "X0"), vreg(t, "X1"), vreg(t, "X2")}, "c4e2f1a9d0", ""},
+		{"VFNMADD231SD X0,X1,X2", "VFNMADD231SD", []Operand{vreg(t, "X0"), vreg(t, "X1"), vreg(t, "X2")}, "c4e2f1bdd0", ""},
+		// Packed single XOR and byte compare (NDS form).
+		{"VXORPS Y0,Y1,Y2", "VXORPS", []Operand{vreg(t, "Y0"), vreg(t, "Y1"), vreg(t, "Y2")}, "c5f457d0", ""},
+		{"VPCMPEQB Y0,Y1,Y2", "VPCMPEQB", []Operand{vreg(t, "Y0"), vreg(t, "Y1"), vreg(t, "Y2")}, "c5f574d0", ""},
+		// Octa byte shifts (vvvv carries the destination).
+		{"VPSLLDQ $2,X0,X1", "VPSLLDQ", []Operand{Imm(2), vreg(t, "X0"), vreg(t, "X1")}, "c5f173f802", ""},
+		{"VPSRLDQ $2,Y0,Y1", "VPSRLDQ", []Operand{Imm(2), vreg(t, "Y0"), vreg(t, "Y1")}, "c5f573d802", ""},
+		// Two-source shuffle, blend and carry-less multiply (NDS + imm8).
+		{"VPERM2F128 $3,Y0,Y1,Y2", "VPERM2F128", []Operand{Imm(3), vreg(t, "Y0"), vreg(t, "Y1"), vreg(t, "Y2")}, "c4e37506d003", ""},
+		{"VPBLENDD $3,X0,X1,X2", "VPBLENDD", []Operand{Imm(3), vreg(t, "X0"), vreg(t, "X1"), vreg(t, "X2")}, "c4e37102d003", ""},
+		{"VPBLENDD $3,Y0,Y1,Y2", "VPBLENDD", []Operand{Imm(3), vreg(t, "Y0"), vreg(t, "Y1"), vreg(t, "Y2")}, "c4e37502d003", ""},
+		{"VPCLMULQDQ $0,X0,X1,X2", "VPCLMULQDQ", []Operand{Imm(0), vreg(t, "X0"), vreg(t, "X1"), vreg(t, "X2")}, "c4e37144d000", ""},
+		{"VGF2P8AFFINEQB $0,X0,X1,X2", "VGF2P8AFFINEQB", []Operand{Imm(0), vreg(t, "X0"), vreg(t, "X1"), vreg(t, "X2")}, "c4e3f1ced000", ""},
+		// Two-operand test and the non-temporal and broadcast stores.
+		{"VPTEST X0,X1", "VPTEST", []Operand{vreg(t, "X0"), vreg(t, "X1")}, "c4e27917c8", ""},
+		{"VPTEST Y0,Y1", "VPTEST", []Operand{vreg(t, "Y0"), vreg(t, "Y1")}, "c4e27d17c8", ""},
+		{"VMOVNTDQ Y0,(AX)", "VMOVNTDQ", []Operand{vreg(t, "Y0"), Ptr(AX, 0, 32)}, "c5fde700", ""},
+		{"VMOVNTDQ X0,(AX)", "VMOVNTDQ", []Operand{vreg(t, "X0"), Ptr(AX, 0, 16)}, "c5f9e700", ""},
+		{"VBROADCASTI128 (AX),Y1", "VBROADCASTI128", []Operand{Ptr(AX, 0, 16), vreg(t, "Y1")}, "c4e27d5a08", ""},
+		// Aligned integer move and the full zeroing form.
+		{"VMOVDQA X0,X1", "VMOVDQA", []Operand{vreg(t, "X0"), vreg(t, "X1")}, "c5f97fc1", ""},
+		{"VMOVDQA (AX),X1", "VMOVDQA", []Operand{Ptr(AX, 0, 16), vreg(t, "X1")}, "c5f96f08", ""},
+		{"VMOVDQA Y0,Y1", "VMOVDQA", []Operand{vreg(t, "Y0"), vreg(t, "Y1")}, "c5fd7fc1", ""},
+		{"VZEROALL", "VZEROALL", []Operand{}, "c5fc77", ""},
+		// BMI1/BMI2 general-register VEX forms.
+		{"ANDNL AX,BX,CX", "ANDNL", []Operand{AX, BX, CX}, "c4e260f2c8", ""},
+		{"ANDNQ AX,BX,CX", "ANDNQ", []Operand{AX, BX, CX}, "c4e2e0f2c8", ""},
+		{"MULXL AX,BX,CX", "MULXL", []Operand{AX, BX, CX}, "c4e263f6c8", ""},
+		{"MULXQ AX,BX,CX", "MULXQ", []Operand{AX, BX, CX}, "c4e2e3f6c8", ""},
+		{"RORXL $3,AX,CX", "RORXL", []Operand{Imm(3), AX, CX}, "c4e37bf0c803", ""},
+		{"RORXQ $3,AX,CX", "RORXQ", []Operand{Imm(3), AX, CX}, "c4e3fbf0c803", ""},
 		// Two-operand reg/rm form (v̄vvv must be 1111).
 		{"VPMOVSXDQ X0,Y4", "VPMOVSXDQ", []Operand{vreg(t, "X0"), vreg(t, "Y4")}, "c4e27d25e0", ""},
 		{"VPMOVSXWD (SI),Y0", "VPMOVSXWD", []Operand{Ptr(SI, 0, 8), vreg(t, "Y0")}, "c4e27d2306", ""},
@@ -287,6 +340,12 @@ func TestVexGroundTruth(t *testing.T) {
 		}
 		inst, err := x86asm.Decode(code, 64)
 		if err != nil {
+			// The decoder's AVX/BMI table lacks a few rows the Go
+			// assembler emits (the GPR VEX forms and the scalar FMA
+			// spellings); their bytes are the ground truth here.
+			if x86asmUnrecognised[c.mnem] {
+				continue
+			}
 			t.Errorf("%s: Decode(% x): %v", c.name, code, err)
 			continue
 		}