diff --git a/arch/arm64_ext.go b/arch/arm64_ext.go
index 4b0376a..3f0638a 100644
--- a/arch/arm64_ext.go
+++ b/arch/arm64_ext.go
@@ -3785,6 +3785,18 @@ var arm64Extensions = []ExtInstr{
 	{Name: "ZBF2CVTLT", Summary: "Convert BFloat16 pairs from bytes to halfwords, top, no rounding",
 		Word: 0x65093c00, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
 		Ref: "ARM DDI 0487J SVE2: ZBF2CVTLT; inst_gen.go + arm64sveenc.s"},
+	{Name: "ZF1CVT", Summary: "Convert FP8 byte pairs to halfwords, bottom",
+		Word: 0x65083000, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
+		Ref: "ARM DDI 0487J SVE2: F1CVT; inst_gen.go + arm64sveenc.s"},
+	{Name: "ZF1CVTLT", Summary: "Convert FP8 byte pairs to halfwords, bottom, no rounding",
+		Word: 0x65093000, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
+		Ref: "ARM DDI 0487J SVE2: F1CVTLT; inst_gen.go + arm64sveenc.s"},
+	{Name: "ZF2CVT", Summary: "Convert FP8 byte pairs to halfwords, top",
+		Word: 0x65083400, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
+		Ref: "ARM DDI 0487J SVE2: F2CVT; inst_gen.go + arm64sveenc.s"},
+	{Name: "ZF2CVTLT", Summary: "Convert FP8 byte pairs to halfwords, top, no rounding",
+		Word: 0x65093400, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
+		Ref: "ARM DDI 0487J SVE2: F2CVTLT; inst_gen.go + arm64sveenc.s"},
 	{Name: "ZBFADD", Summary: "Add BFloat16 halfwords, merging",
 		Word: 0x65008000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
 		Ref: "ARM DDI 0487J SVE2: ZBFADD; inst_gen.go + arm64sveenc.s"},
diff --git a/arch/arm64_ext_test.go b/arch/arm64_ext_test.go
index b62b9c6..91fc23f 100644
--- a/arch/arm64_ext_test.go
+++ b/arch/arm64_ext_test.go
@@ -1528,6 +1528,18 @@ func TestArm64ExtStage4Golden(t *testing.T) {
 		{"ZBF2CVTLT Z11.B, Z6.H", "ZBF2CVTLT", ExtFormZUnpack, ExtQualNone, ExtArrH,
 			[]ExtOperand{ExtVector(11, ExtArrB), ExtVector(6, ExtArrH)},
 			0x65093d66},
+		{"ZF1CVT Z11.B, Z6.H", "ZF1CVT", ExtFormZUnpack, ExtQualNone, ExtArrH,
+			[]ExtOperand{ExtVector(11, ExtArrB), ExtVector(6, ExtArrH)},
+			0x65083166},
+		{"ZF1CVTLT Z11.B, Z6.H", "ZF1CVTLT", ExtFormZUnpack, ExtQualNone, ExtArrH,
+			[]ExtOperand{ExtVector(11, ExtArrB), ExtVector(6, ExtArrH)},
+			0x65093166},
+		{"ZF2CVT Z11.B, Z6.H", "ZF2CVT", ExtFormZUnpack, ExtQualNone, ExtArrH,
+			[]ExtOperand{ExtVector(11, ExtArrB), ExtVector(6, ExtArrH)},
+			0x65083566},
+		{"ZF2CVTLT Z11.B, Z6.H", "ZF2CVTLT", ExtFormZUnpack, ExtQualNone, ExtArrH,
+			[]ExtOperand{ExtVector(11, ExtArrB), ExtVector(6, ExtArrH)},
+			0x65093566},
 		{"ZBFADD Z23.H, Z13.H, P1.M, Z13.H", "ZBFADD", ExtFormZPredicatedSource, ExtQualMerging, ExtArrH,
 			[]ExtOperand{ExtVector(23, ExtArrH), ExtVector(13, ExtArrH), ExtPredicate(1, ExtQualMerging), ExtVector(13, ExtArrH)},
 			0x650086ed},
diff --git a/asm/arm64_ext_asm_test.go b/asm/arm64_ext_asm_test.go
index 7207471..7c6501f 100644
--- a/asm/arm64_ext_asm_test.go
+++ b/asm/arm64_ext_asm_test.go
@@ -814,6 +814,10 @@ func TestArm64AssembleExtensionStage4Golden(t *testing.T) {
 		{"ZBF1CVTLT Z11.B, Z6.H", 0x65093966},
 		{"ZBF2CVT Z11.B, Z6.H", 0x65083d66},
 		{"ZBF2CVTLT Z11.B, Z6.H", 0x65093d66},
+		{"ZF1CVT Z11.B, Z6.H", 0x65083166},
+		{"ZF1CVTLT Z11.B, Z6.H", 0x65093166},
+		{"ZF2CVT Z11.B, Z6.H", 0x65083566},
+		{"ZF2CVTLT Z11.B, Z6.H", 0x65093566},
 		{"ZBFADD Z23.H, Z13.H, P1.M, Z13.H", 0x650086ed},
 		{"ZBFADD Z7.H, Z6.H, Z23.H", 0x650700d7},
 		{"ZBFCLAMP Z7.H, Z6.H, Z23.H", 0x642724d7},
diff --git a/asm/extension_test.go b/asm/extension_test.go
index 7e74bbc..8383ec6 100644
--- a/asm/extension_test.go
+++ b/asm/extension_test.go
@@ -321,6 +321,10 @@ func TestExtensionNamesARM64(t *testing.T) {
 		"ZBF1CVTLT",
 		"ZBF2CVT",
 		"ZBF2CVTLT",
+		"ZF1CVT",
+		"ZF1CVTLT",
+		"ZF2CVT",
+		"ZF2CVTLT",
 		"ZBFADD",
 		"ZBFCLAMP",
 		"ZBFMAX",
@@ -493,7 +497,7 @@ func TestExtensionNamesARM64(t *testing.T) {
 	if strings.Join(got, ",") != strings.Join(want, ",") {
 		t.Errorf("ExtensionNames(ARM64) = %v, want %v", got, want)
 	}
-	if n := len(arch.Extensions(arch.ARM64)); n != 503 {
-		t.Errorf("the family registers %d instructions, want 503", n)
+	if n := len(arch.Extensions(arch.ARM64)); n != 507 {
+		t.Errorf("the family registers %d instructions, want 507", n)
 	}
 }