feat(asm): split wide arm64 load and store offsets into REGTMP

Offsets the single-instruction forms cannot carry lower the way the
toolchain lowers them: ADD or SUB moves the whole distance into REGTMP
within the ±4095 band, and the 24-bit band above it splits into an ADD of
the high half and an access of the low half, with the pair family taking
the two-ADD sequence.  The split band follows loadStoreClass per width,
byte accesses taking the full 24 bits and the Q width the widest, so an
offset the toolchain pools is never split instead.

Assisted-by: GLM 5.3 Flash

testdata/verify/splits_arm64.s

@@ -0,0 +1,57 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+// Differential kernel for the arm64 out-of-band offsets: the ADD/SUB into
+// REGTMP for offsets within ±4095 no single instruction carries, and the
+// 24-bit hi/lo split for the wide bands.  Every function is byte-compared
+// against go tool asm.
+
+#include "textflag.h"
+
+// func bytes()
+TEXT ·bytes(SB), NOSPLIT, $0-0
+	MOVB R1, 4096(R2)
+	MOVB R1, 8190(R2)
+	MOVB R1, 65520(R2)
+	MOVB R1, -4095(R2)
+	MOVB 4096(R2), R1
+	RET
+
+// func halves()
+TEXT ·halves(SB), NOSPLIT, $0-0
+	MOVH R1, 16384(R2)
+	MOVH R1, 16781310(R2)
+	MOVH 0x2002(R1), R2
+	MOVH R1, -4095(R2)
+	RET
+
+// func words()
+TEXT ·words(SB), NOSPLIT, $0-0
+	MOVW R1, 16388(R2)
+	MOVW 0x4004(R1), R2
+	MOVD R1, 4094(R2)
+	MOVD R1, -300(R2)
+	MOVD R1, 0x1006ff8(R2)
+	MOVD 0x1006ff8(R1), R2
+	FMOVS F1, 0x4004(R2)
+	FMOVD F1, 0x1006ff8(R1)
+	FMOVQ F1, 0x1003000(R2)
+	RET
+
+// func pairs()
+TEXT ·pairs(SB), NOSPLIT, $0-0
+	STP (R3, R4), 11(R0)
+	STP (R3, R4), 1024(R0)
+	STP (R3, R4), -4(R5)
+	STP (R3, R4), 65536(R2)
+	STPW (R3, R4), 1024(R0)
+	LDP 11(R0), (R1, R2)
+	LDP 1024(R0), (R1, R2)
+	LDP -31(R0), (R1, R2)
+	LDP 65536(R2), (R1, R2)
+	LDPW -5(R0), (R1, R2)
+	LDPSW 1024(R0), (R1, R2)
+	FLDPD 1024(R0), (F1, F2)
+	FLDPQ 1024(R0), (F1, F2)
+	FLDPS 1024(R0), (F1, F2)
+	RET