feat(asm): encode the riscv64 vector arithmetic families
Assisted-by: GLM 5.3 Flash
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petrbalvin committed
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@@ -3636,88 +3636,571 @@ func encodeRISCVVector(mnem string, ops []*ast.Operand) ([]byte, bool, error) {
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// (0xcd07f657) from GOARCH=riscv64 go tool asm.
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ivli := mnem == "VSETIVLI" || isImmOperand(ops[0])
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return wordLE(riscvVSetEnc(ivli, avl, riscvVType(vsew, vlmul, vta, vma), rd)), true, nil
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case "VADDVV", "VXORVV", "VMSNEVV":
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// Vector-vector: INSTR vs1, vs2, vd.
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if len(ops) != 3 {
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return nil, true, fmt.Errorf("%s expects 3 operands, got %d", mnem, len(ops))
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}
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vs1, vs2, vd := reg(ops[0]), reg(ops[1]), reg(ops[2])
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if vs1 < 0 || vs2 < 0 || vd < 0 {
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return nil, true, fmt.Errorf("%s: invalid vector register", mnem)
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}
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funct6 := map[string]int{"VADDVV": 0x00, "VXORVV": 0x0B, "VMSNEVV": 0x19}[mnem]
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return wordLE(riscvVVInstr(funct6, riscvVf3VV, int32(vs1), vs2, vd)), true, nil
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case "VADDVX", "VMSEQVX":
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// Vector-scalar: INSTR rs1, vs2, vd (the scalar in the rs1 field).
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if len(ops) != 3 {
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return nil, true, fmt.Errorf("%s expects 3 operands, got %d", mnem, len(ops))
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}
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rs1, vs2, vd := reg(ops[0]), reg(ops[1]), reg(ops[2])
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if rs1 < 0 || vs2 < 0 || vd < 0 {
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return nil, true, fmt.Errorf("%s: invalid register operand", mnem)
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}
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funct6 := 0x00
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if mnem == "VMSEQVX" {
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funct6 = 0x18
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}
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return wordLE(riscvVVInstr(funct6, riscvVf3VX, int32(rs1), vs2, vd)), true, nil
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case "VSLLVI", "VSRLVI":
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// Vector-immediate shift: INSTR $uimm, vs2, vd.
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if len(ops) != 3 {
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return nil, true, fmt.Errorf("%s expects 3 operands, got %d", mnem, len(ops))
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}
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imm := int(immFromOperand(ops[0]))
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if imm < 0 || imm > 31 {
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return nil, true, fmt.Errorf("%s: immediate out of range [0, 31]", mnem)
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}
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vs2, vd := reg(ops[1]), reg(ops[2])
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if vs2 < 0 || vd < 0 {
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return nil, true, fmt.Errorf("%s: invalid vector register", mnem)
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}
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funct6 := 0x25 // vsll.vi
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if mnem == "VSRLVI" {
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funct6 = 0x28 // vsrl.vi
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}
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return wordLE(riscvVVInstr(funct6, riscvVf3VI, int32(imm), vs2, vd)), true, nil
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case "VFIRSTM":
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// vmfirst.m rd, vs2: the unmasked form carries 0x11 in the rs1 field
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// and sets the mask bit (funct7 = 0x20 | 1).
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if len(ops) != 2 {
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return nil, true, fmt.Errorf("VFIRSTM expects 2 operands, got %d", len(ops))
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}
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vs2, rd := reg(ops[0]), reg(ops[1])
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if vs2 < 0 || rd < 0 {
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return nil, true, fmt.Errorf("VFIRSTM: invalid register operand")
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}
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return wordLE(riscvVUnaryInstr(0x10, riscvVf3MV, 0x11, vs2, rd)), true, nil
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case "VIDV":
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// vid.v vd (vs2 must be v0; the unmasked form sets the mask bit).
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if len(ops) != 1 {
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return nil, true, fmt.Errorf("VIDV expects 1 operand, got %d", len(ops))
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}
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vd := reg(ops[0])
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if vd < 0 {
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return nil, true, fmt.Errorf("VIDV: invalid vector register")
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}
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return wordLE(riscvVUnaryInstr(0x14, riscvVf3MV, 0x11, 0, vd)), true, nil
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case "VMV4RV":
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// vmv4r.v vd, vs2: whole-register group move.
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if len(ops) != 2 {
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return nil, true, fmt.Errorf("VMV4RV expects 2 operands, got %d", len(ops))
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}
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vs2, vd := reg(ops[0]), reg(ops[1])
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if vs2 < 0 || vd < 0 {
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return nil, true, fmt.Errorf("VMV4RV: invalid vector register")
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}
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return wordLE(riscvVUnaryInstr(0x27, 0x3, 0x3, vs2, vd)), true, nil
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}
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return nil, false, nil
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// Every remaining OP-V mnemonic the toolchain knows: the arithmetic
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// table, dispatched by operand class.
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return encodeRISCVVecOp(mnem, ops)
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}
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// encodeRISCVVecOp encodes one vector arithmetic instruction through the
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// extracted table. The entry's class places the operands in the rs1 and vs2
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// fields, an optional V0 between the sources and the destination clears the
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// vm bit, and the transform classes rewrite the pseudo forms the toolchain
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// expands before encoding (the swapped comparisons, VNEGV and friends).
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func encodeRISCVVecOp(mnem string, ops []*ast.Operand) ([]byte, bool, error) {
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op, ok := riscvVecOps[mnem]
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if !ok {
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return nil, false, nil
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}
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// vecReg reads a register operand; what names the field in the error.
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vecReg := func(o *ast.Operand, what string) (int, error) {
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r := regFromOperand(o)
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if r < 0 {
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return 0, fmt.Errorf("%s: invalid %s", mnem, what)
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}
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return r, nil
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}
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// vecImm reads the immediate the entry's form bounds: signed five bits
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// [-16, 15], or unsigned [0, 31] for the shifts and slides.
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vecImm := func(o *ast.Operand) (int32, error) {
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if !isImmOperand(o) {
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return 0, fmt.Errorf("%s expects an immediate first operand", mnem)
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}
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v := immFromOperand(o)
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if op.immU {
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if v < 0 || v > 31 {
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return 0, fmt.Errorf("%s: immediate %d out of range [0, 31]", mnem, v)
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}
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} else if v < -16 || v > 15 {
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return 0, fmt.Errorf("%s: immediate %d out of range [-16, 15]", mnem, v)
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}
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return int32(v), nil
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}
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// vecMask reads the optional mask operand: only V0 is lawful.
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vecMask := func(o *ast.Operand) error {
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if regFromOperand(o) != 0 {
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return fmt.Errorf("%s: the vector mask register must be V0", mnem)
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}
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return nil
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}
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// vm carries the funct7 with the vm bit set for the unmasked form: the
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// toolchain ORs 1 when no V0 follows the sources.
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vm := func(masked bool) uint32 {
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if !masked {
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return op.funct7 | 1
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}
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return op.funct7
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}
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// word builds the instruction from the entry's fields.
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word := func(funct7 uint32, rs1Field int32, vs2 int, funct3 uint32, vd int) ([]byte, bool, error) {
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return wordLE(riscvVecWord(funct7, rs1Field, vs2, funct3, vd)), true, nil
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}
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// rename resolves a transform to its target table entry.
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rename := func(to string) (riscvVecOp, error) {
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t, ok := riscvVecOps[to]
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if !ok {
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return riscvVecOp{}, fmt.Errorf("%s: transform target %q not in the table", mnem, to)
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}
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return t, nil
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}
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switch op.class {
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case vecVV:
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// INSTR vs1|$imm, vs2 [, V0], vd.
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if len(ops) != 3 && len(ops) != 4 {
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return nil, true, fmt.Errorf("%s expects 3 or 4 operands, got %d", mnem, len(ops))
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}
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masked := len(ops) == 4
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if masked {
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if err := vecMask(ops[2]); err != nil {
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return nil, true, err
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}
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}
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vs2, err := vecReg(ops[1], "vs2")
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if err != nil {
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return nil, true, err
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}
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vd, err := vecReg(ops[len(ops)-1], "vd")
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if err != nil {
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return nil, true, err
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}
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var rs1Field int32
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if op.imm {
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if rs1Field, err = vecImm(ops[0]); err != nil {
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return nil, true, err
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}
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} else {
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var vs1 int
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if vs1, err = vecReg(ops[0], "vs1"); err != nil {
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return nil, true, err
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}
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rs1Field = int32(vs1)
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}
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return word(vm(masked), rs1Field, vs2, op.funct3, vd)
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case vecMACC:
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// INSTR vs2, vs1 [, V0], vd: the multiply-accumulate order, the
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// addend in the rs1 field and the multiplicand in vs2.
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if len(ops) != 3 && len(ops) != 4 {
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return nil, true, fmt.Errorf("%s expects 3 or 4 operands, got %d", mnem, len(ops))
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}
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masked := len(ops) == 4
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if masked {
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if err := vecMask(ops[2]); err != nil {
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return nil, true, err
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}
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}
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vs2, err := vecReg(ops[0], "vs2")
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if err != nil {
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return nil, true, err
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}
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vd, err := vecReg(ops[len(ops)-1], "vd")
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if err != nil {
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return nil, true, err
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}
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var rs1Field int32
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if op.imm {
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if rs1Field, err = vecImm(ops[1]); err != nil {
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return nil, true, err
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}
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} else {
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var vs1 int
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if vs1, err = vecReg(ops[1], "vs1"); err != nil {
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return nil, true, err
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}
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rs1Field = int32(vs1)
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}
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return word(vm(masked), rs1Field, vs2, op.funct3, vd)
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case vecSWAPVV:
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// VMSGT*/VMSGE*/VMFGT*/VMFGE* swap the two sources and lower to the
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// VMSLT*/VMSLE*/VMFLT*/VMFLE* entries the table carries.
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if len(ops) != 3 && len(ops) != 4 {
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return nil, true, fmt.Errorf("%s expects 3 or 4 operands, got %d", mnem, len(ops))
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}
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masked := len(ops) == 4
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if masked {
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if err := vecMask(ops[2]); err != nil {
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return nil, true, err
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}
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}
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t, err := rename(map[string]string{
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"VMSGTVV": "VMSLTVV", "VMSGTUVV": "VMSLTUVV",
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"VMSGEVV": "VMSLEVV", "VMSGEUVV": "VMSLEUVV",
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"VMFGTVV": "VMFLTVV", "VMFGEVV": "VMFLEVV",
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}[mnem])
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if err != nil {
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return nil, true, err
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}
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vs2, err := vecReg(ops[0], "vs2")
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if err != nil {
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return nil, true, err
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}
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vd, err := vecReg(ops[len(ops)-1], "vd")
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if err != nil {
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return nil, true, err
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}
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vs1, err := vecReg(ops[1], "vs1")
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if err != nil {
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return nil, true, err
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}
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f7 := t.funct7
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if !masked {
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f7 |= 1
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}
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return word(f7, int32(vs1), vs2, t.funct3, vd)
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case vecSWAPVI:
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// VMSLTVI and the VMSGE*VI forms subtract one from the immediate and
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// lower to the VMSLE*/VMSGT* entries.
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if len(ops) != 3 && len(ops) != 4 {
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return nil, true, fmt.Errorf("%s expects 3 or 4 operands, got %d", mnem, len(ops))
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}
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masked := len(ops) == 4
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if masked {
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if err := vecMask(ops[2]); err != nil {
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return nil, true, err
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}
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}
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t, err := rename(map[string]string{
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"VMSLTVI": "VMSLEVI", "VMSLTUVI": "VMSLEUVI",
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"VMSGEVI": "VMSGTVI", "VMSGEUVI": "VMSGTUVI",
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}[mnem])
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if err != nil {
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return nil, true, err
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}
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imm, err := vecImm(ops[0])
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if err != nil {
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return nil, true, err
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}
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imm--
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if imm < -16 || imm > 15 {
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return nil, true, fmt.Errorf("%s: immediate %d leaves [-16, 15] after the swap", mnem, imm+1)
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}
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vs2, err := vecReg(ops[1], "vs2")
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if err != nil {
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return nil, true, err
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}
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vd, err := vecReg(ops[len(ops)-1], "vd")
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if err != nil {
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return nil, true, err
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}
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f7 := t.funct7
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if !masked {
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f7 |= 1
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}
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return word(f7, imm, vs2, t.funct3, vd)
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case vecUNARY, vecM2I:
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// INSTR vs2 [, V0], vd: one vector source, the fixed rs1 field; the
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// m2i members take the destination in the integer file.
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if len(ops) != 2 && len(ops) != 3 {
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return nil, true, fmt.Errorf("%s expects 2 or 3 operands, got %d", mnem, len(ops))
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}
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masked := len(ops) == 3
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if masked {
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if err := vecMask(ops[1]); err != nil {
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return nil, true, err
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}
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}
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vs2, err := vecReg(ops[0], "vs2")
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if err != nil {
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return nil, true, err
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}
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vd, err := vecReg(ops[len(ops)-1], "vd")
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if err != nil {
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return nil, true, err
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}
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return word(vm(masked), int32(op.rs1), vs2, op.funct3, vd)
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case vecNEG:
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// VNEGV, VWCVTXXV, VWCVTUXXV and VNCVTXXW read as one-operand forms
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// of VRSUBVX, VWADDVX, VWADDUVX and VNSRLWX with X0 in the rs1 field.
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if len(ops) != 2 && len(ops) != 3 {
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return nil, true, fmt.Errorf("%s expects 2 or 3 operands, got %d", mnem, len(ops))
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}
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masked := len(ops) == 3
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if masked {
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if err := vecMask(ops[1]); err != nil {
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return nil, true, err
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}
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}
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t, err := rename(map[string]string{
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"VNEGV": "VRSUBVX", "VWCVTXXV": "VWADDVX",
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"VWCVTUXXV": "VWADDUVX", "VNCVTXXW": "VNSRLWX",
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}[mnem])
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if err != nil {
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return nil, true, err
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}
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vs2, err := vecReg(ops[0], "vs2")
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if err != nil {
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return nil, true, err
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}
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vd, err := vecReg(ops[len(ops)-1], "vd")
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if err != nil {
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return nil, true, err
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}
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f7 := t.funct7
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if !masked {
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f7 |= 1
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}
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return word(f7, 0, vs2, t.funct3, vd)
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case vecVNOT:
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// VNOTV reads as VXORVI with the all-ones immediate.
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if len(ops) != 2 && len(ops) != 3 {
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return nil, true, fmt.Errorf("%s expects 2 or 3 operands, got %d", mnem, len(ops))
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}
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masked := len(ops) == 3
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if masked {
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if err := vecMask(ops[1]); err != nil {
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return nil, true, err
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}
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}
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t, err := rename("VXORVI")
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if err != nil {
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return nil, true, err
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}
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vs2, err := vecReg(ops[0], "vs2")
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if err != nil {
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return nil, true, err
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}
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vd, err := vecReg(ops[len(ops)-1], "vd")
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if err != nil {
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return nil, true, err
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}
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f7 := t.funct7
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if !masked {
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f7 |= 1
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}
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return word(f7, -1, vs2, t.funct3, vd)
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case vecVFABS:
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// VFABSV and VFNEGV read as VFSGNJXVV/VFSGNJNVVV with the source in
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// both the rs1 and vs2 fields.
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if len(ops) != 2 && len(ops) != 3 {
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return nil, true, fmt.Errorf("%s expects 2 or 3 operands, got %d", mnem, len(ops))
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}
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masked := len(ops) == 3
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if masked {
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if err := vecMask(ops[1]); err != nil {
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return nil, true, err
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}
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}
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t, err := rename(map[string]string{
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"VFABSV": "VFSGNJXVV", "VFNEGV": "VFSGNJNVV",
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}[mnem])
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if err != nil {
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return nil, true, err
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}
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vs2, err := vecReg(ops[0], "vs2")
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if err != nil {
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return nil, true, err
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}
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vd, err := vecReg(ops[len(ops)-1], "vd")
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if err != nil {
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return nil, true, err
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}
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f7 := t.funct7
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if !masked {
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f7 |= 1
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}
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return word(f7, int32(vs2), vs2, t.funct3, vd)
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case vecVMVV:
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// INSTR vs2, vd (vmv.v.v/vmv.v.x): the source in the rs1 field, V0
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// fixed in vs2, the vm bit from the table.
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if len(ops) != 2 {
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return nil, true, fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
|
||||
}
|
||||
vs2, err := vecReg(ops[0], "vs2")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
vd, err := vecReg(ops[1], "vd")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
return word(op.funct7, int32(vs2), 0, op.funct3, vd)
|
||||
|
||||
case vecVMVI:
|
||||
// INSTR $imm, vd (vmv.v.i): the immediate in the rs1 field, V0 in
|
||||
// vs2, the vm bit from the table.
|
||||
if len(ops) != 2 {
|
||||
return nil, true, fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
|
||||
}
|
||||
imm, err := vecImm(ops[0])
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
vd, err := vecReg(ops[1], "vd")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
return word(op.funct7, imm, 0, op.funct3, vd)
|
||||
|
||||
case vecVFMVVF:
|
||||
// INSTR fs1, vd (vfmv.v.f): the scalar in the rs1 field, V0 in vs2.
|
||||
if len(ops) != 2 {
|
||||
return nil, true, fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
|
||||
}
|
||||
fs1, err := vecReg(ops[0], "fs1")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
vd, err := vecReg(ops[1], "vd")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
return word(op.funct7, int32(fs1), 0, op.funct3, vd)
|
||||
|
||||
case vecTWO:
|
||||
// INSTR vs2, vd: two-operand forms with the fixed rs1 field (the
|
||||
// extensions and conversions, the whole-register moves, the scalar
|
||||
// reads).
|
||||
if len(ops) != 2 {
|
||||
return nil, true, fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
|
||||
}
|
||||
vs2, err := vecReg(ops[0], "vs2")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
vd, err := vecReg(ops[1], "vd")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
return word(op.funct7, int32(op.rs1), vs2, op.funct3, vd)
|
||||
|
||||
case vecTWOX:
|
||||
// INSTR xs1|fs1, vd: two-operand forms with the fixed vs2 field
|
||||
// (vmv.s.x and vfmv.s.f).
|
||||
if len(ops) != 2 {
|
||||
return nil, true, fmt.Errorf("%s expects 2 operands, got %d", mnem, len(ops))
|
||||
}
|
||||
rs1, err := vecReg(ops[0], "rs1")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
vd, err := vecReg(ops[1], "vd")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
return word(op.funct7, int32(rs1), int(op.rs1), op.funct3, vd)
|
||||
|
||||
case vecADC:
|
||||
// INSTR vs1|$imm, vs2, V0, vd: the carry forms, the mask mandatory,
|
||||
// V0 rejected as the destination.
|
||||
if len(ops) != 4 {
|
||||
return nil, true, fmt.Errorf("%s expects 4 operands, got %d", mnem, len(ops))
|
||||
}
|
||||
if err := vecMask(ops[2]); err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
vs2, err := vecReg(ops[1], "vs2")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
vd, err := vecReg(ops[3], "vd")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
if vd == 0 {
|
||||
return nil, true, fmt.Errorf("%s: invalid destination register V0", mnem)
|
||||
}
|
||||
var rs1Field int32
|
||||
if op.imm {
|
||||
if rs1Field, err = vecImm(ops[0]); err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
} else {
|
||||
var vs1 int
|
||||
if vs1, err = vecReg(ops[0], "vs1"); err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
rs1Field = int32(vs1)
|
||||
}
|
||||
return word(op.funct7, rs1Field, vs2, op.funct3, vd)
|
||||
|
||||
case vecMERGE:
|
||||
// INSTR vs1|fs1|$imm, vs2, V0, vd: the merge forms, the mask
|
||||
// mandatory, V0 allowed as the destination.
|
||||
if len(ops) != 4 {
|
||||
return nil, true, fmt.Errorf("%s expects 4 operands, got %d", mnem, len(ops))
|
||||
}
|
||||
if err := vecMask(ops[2]); err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
vs2, err := vecReg(ops[1], "vs2")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
vd, err := vecReg(ops[3], "vd")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
var rs1Field int32
|
||||
if op.imm {
|
||||
if rs1Field, err = vecImm(ops[0]); err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
} else {
|
||||
var vs1 int
|
||||
if vs1, err = vecReg(ops[0], "vs1"); err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
rs1Field = int32(vs1)
|
||||
}
|
||||
return word(op.funct7, rs1Field, vs2, op.funct3, vd)
|
||||
|
||||
case vecVMADC:
|
||||
// INSTR vs1|$imm, vs2, vd: the carry-producing forms; the third
|
||||
// operand names the destination and may be V0.
|
||||
if len(ops) != 3 {
|
||||
return nil, true, fmt.Errorf("%s expects 3 operands, got %d", mnem, len(ops))
|
||||
}
|
||||
vs2, err := vecReg(ops[1], "vs2")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
vd, err := vecReg(ops[2], "vd")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
var rs1Field int32
|
||||
if op.imm {
|
||||
if rs1Field, err = vecImm(ops[0]); err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
} else {
|
||||
var vs1 int
|
||||
if vs1, err = vecReg(ops[0], "vs1"); err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
rs1Field = int32(vs1)
|
||||
}
|
||||
return word(op.funct7, rs1Field, vs2, op.funct3, vd)
|
||||
|
||||
case vecMM:
|
||||
// INSTR vs1, vs2, vd: the mask-mask forms. VMMVM and VMNOTM take
|
||||
// two operands and fold the second source into the first; the vm
|
||||
// bit stays as the table carries it.
|
||||
folded := mnem == "VMMVM" || mnem == "VMNOTM"
|
||||
if (folded && len(ops) != 2) || (!folded && len(ops) != 3) {
|
||||
return nil, true, fmt.Errorf("%s expects %d operands, got %d", mnem, map[bool]int{true: 2, false: 3}[folded], len(ops))
|
||||
}
|
||||
vs1, err := vecReg(ops[0], "vs1")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
vs2 := vs1
|
||||
if !folded {
|
||||
if vs2, err = vecReg(ops[1], "vs2"); err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
}
|
||||
vd, err := vecReg(ops[len(ops)-1], "vd")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
return word(op.funct7, int32(vs1), vs2, op.funct3, vd)
|
||||
|
||||
case vecVMCLR:
|
||||
// INSTR vd: the whole-mask clears and sets, one register in all
|
||||
// three fields.
|
||||
if len(ops) != 1 {
|
||||
return nil, true, fmt.Errorf("%s expects 1 operand, got %d", mnem, len(ops))
|
||||
}
|
||||
t, err := rename(map[string]string{
|
||||
"VMCLRM": "VMXORMM", "VMSETM": "VMXNORMM",
|
||||
}[mnem])
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
r, err := vecReg(ops[0], "vd")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
return word(t.funct7, int32(r), r, t.funct3, r)
|
||||
|
||||
case vecVID:
|
||||
// INSTR [V0,] vd: the element index, the mask before the destination.
|
||||
if len(ops) != 1 && len(ops) != 2 {
|
||||
return nil, true, fmt.Errorf("%s expects 1 or 2 operands, got %d", mnem, len(ops))
|
||||
}
|
||||
masked := len(ops) == 2
|
||||
if masked {
|
||||
if err := vecMask(ops[0]); err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
}
|
||||
vd, err := vecReg(ops[len(ops)-1], "vd")
|
||||
if err != nil {
|
||||
return nil, true, err
|
||||
}
|
||||
return word(vm(masked), int32(op.rs1), 0, op.funct3, vd)
|
||||
}
|
||||
return nil, true, fmt.Errorf("%s: unhandled vector operand class", mnem)
|
||||
}
|
||||
|
||||
// riscvVTypeToken parses a vsetvli configuration token (E8, M8, MF2 and
|
||||
|
||||
Reference in new issue
Block a user