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feat(asm): encode the riscv64 vector arithmetic families

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Assisted-by: GLM 5.3 Flash
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petrbalvin committed 2026-10-07 00:47:27 +02:00
1 parent 5de9e985f8
commit 778c297214
3 files changed
+1812 -102
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asm/riscv_encode.go
+436 -21
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@@ -540,11 +540,8 @@ func riscvJType(rd int, offset int32) uint32 {
const (
riscvOpV = 0x57 // the vector operation opcode (also OPcfg for vset*)
// funct3 values: 0 OPIVV, 1 OPFVV, 2 OPMVV, 3 OPIVI, 4 OPIVX,
// 5 OPFVF, 6 OPMVX, 7 vsetvli.
riscvVf3VV = 0x0 // vector-vector
riscvVf3MV = 0x2 // vector mask
riscvVf3VI = 0x3 // vector-immediate
riscvVf3VX = 0x4 // vector-scalar
// 5 OPFVF, 6 OPMVX, 7 vsetvli. The subclass a mnemonic carries lives
// in its table entry's funct3.
riscvVf3Cfg = 0x7 // vsetvli
)
@@ -578,27 +575,445 @@ func riscvVLSType(op uint32, nf, mop, width int, rs2 int32, rs1, rd int) uint32
uint32(rd)<<7 | op
}
// riscvVVInstr encodes an OP-V instruction with the six-bit operation code in
// funct7's upper bits, bit 25 as the unmasked flag and the three registers in
// the standard positions. vs1 may name an integer register for the *VX forms
// (the scalar sits in the rs1 field) or an immediate for the *VI forms.
func riscvVVInstr(funct6, funct3 int, vs1 int32, vs2, vd int) uint32 {
return uint32(funct6&0x3F)<<26 | 1<<25 | uint32(vs1)<<15 |
uint32(funct3)<<12 | uint32(vs2)<<20 | uint32(vd)<<7 | riscvOpV
}
// riscvVUnaryInstr encodes a one-vector-operand OP-V instruction whose fixed
// fields live where the second source register would be: rs1Field and vs2 are
// written verbatim (the oracle writes fixed non-zero constants there for some
// instructions, such as 0x11 in the rs1 field of vmfirst.m and vid.v).
func riscvVUnaryInstr(funct6, funct3 int, rs1Field int32, vs2, vd int) uint32 {
return uint32(funct6&0x3F)<<26 | 1<<25 | uint32(vs2&0x1F)<<20 |
uint32(rs1Field&0x1F)<<15 | uint32(funct3&0x7)<<12 | uint32(vd&0x1F)<<7 | riscvOpV
// riscvVecWord composes one OP-V arithmetic word: funct7 carries funct6 << 1
// with the vm bit in its LSB, exactly as the table stores it; rs1Field takes
// the source register, the scalar or the immediate; vs2 and vd name vector
// registers.
func riscvVecWord(funct7 uint32, rs1Field int32, vs2 int, funct3 uint32, vd int) uint32 {
return funct7<<25 | uint32(vs2&0x1F)<<20 | uint32(rs1Field&0x1F)<<15 |
funct3&0x7<<12 | uint32(vd&0x1F)<<7 | riscvOpV
}
// riscvSegNF maps a segment count to the 3-bit nf field (count - 1).
func riscvSegNF(n int) int32 { return int32(n - 1) }
// The table below mirrors the Go toolchain's own instruction table
// (cmd/internal/obj/riscv): funct7 carries funct6 << 1 with the fixed
// vm bit in its LSB, exactly as the toolchain stores it.
// riscvVecOpClass names the operand shape a vector arithmetic mnemonic
// takes: which operands land in the rs1 and vs2 fields, whether a
// V0 mask may sit between them, and whether the class rewrites its
// operands or its mnemonic before encoding.
type riscvVecOpClass uint8
const (
// vs1, vs2 [, v0], vd: the plain vector-vector form
vecVV riscvVecOpClass = iota
// vs2, vs1 [, v0], vd: the multiply-accumulate order
vecMACC
// vs2 [, v0], vd: one vector operand, fixed rs1
vecUNARY
// vs2 [, v0], xrd: mask bookkeeping into an integer register
vecM2I
// vs2, vd: vmv.v.v and vmv.v.x spellings
vecVMVV
// $imm, vd: vmv.v.i
vecVMVI
// fs1, vd: vfmv.v.f
vecVFMVVF
// vs2, vd: two-operand forms with a fixed rs1 field
vecTWO
// xs1|fs1, vd: two-operand forms with a fixed vs2 field
vecTWOX
// vs1, vs2, v0, vd: the carry forms, mask mandatory
vecADC
// vs1, vs2, v0, vd: the merge forms, mask mandatory
vecMERGE
// vs1, vs2, vd: the carry-producing forms
vecVMADC
// vs2 [, v0], vd with rs1 = x0: VNEGV and friends
vecNEG
// vs2 [, v0], vd: XOR with -1
vecVNOT
// vs2, vs1 [, v0], vd: the swapped comparisons
vecSWAPVV
// $imm, vs2 [, v0], vd: swapped, imm-1
vecSWAPVI
// vs2 [, v0], vd with rs1 = vs2: VFABSV and VFNEGV
vecVFABS
// vs1, vs2, vd: the mask-mask forms, no mask operand
vecMM
// vd: the whole-mask clears and sets
vecVMCLR
// [v0,] vd: the element index
vecVID
)
// riscvVecOp is one vector arithmetic instruction's fixed fields: the
// funct3 subclass, the fixed rs1 field (the unary constants), the fixed
// funct7 (funct6 << 1 with the fixed vm bit), the operand class and the
// immediate form the first operand takes.
type riscvVecOp struct {
funct3 uint32
rs1 uint32
funct7 uint32
class riscvVecOpClass
imm bool // the first operand is an immediate in the rs1 field
immU bool // that immediate is unsigned [0, 31] (shifts and slides)
}
// riscvVecOps maps every vector arithmetic mnemonic the toolchain knows
// onto its fields. The loads and stores and the configuration setters
// have their own paths.
var riscvVecOps = map[string]riscvVecOp{
"VAADDUVV": {0x2, 0x0, 0x10, 0, false, false},
"VAADDUVX": {0x6, 0x0, 0x10, 0, false, false},
"VAADDVV": {0x2, 0x0, 0x12, 0, false, false},
"VAADDVX": {0x6, 0x0, 0x12, 0, false, false},
"VADCVIM": {0x3, 0x0, 0x20, 9, true, false},
"VADCVVM": {0x0, 0x0, 0x20, 9, false, false},
"VADCVXM": {0x4, 0x0, 0x20, 9, false, false},
"VADDVI": {0x3, 0x0, 0x00, 0, true, false},
"VADDVV": {0x0, 0x0, 0x00, 0, false, false},
"VADDVX": {0x4, 0x0, 0x00, 0, false, false},
"VANDNVV": {0x0, 0x0, 0x02, 0, false, false},
"VANDNVX": {0x4, 0x0, 0x02, 0, false, false},
"VANDVI": {0x3, 0x0, 0x12, 0, true, false},
"VANDVV": {0x0, 0x0, 0x12, 0, false, false},
"VANDVX": {0x4, 0x0, 0x12, 0, false, false},
"VASUBUVV": {0x2, 0x0, 0x14, 0, false, false},
"VASUBUVX": {0x6, 0x0, 0x14, 0, false, false},
"VASUBVV": {0x2, 0x0, 0x16, 0, false, false},
"VASUBVX": {0x6, 0x0, 0x16, 0, false, false},
"VBREV8V": {0x2, 0x8, 0x24, 2, false, false},
"VBREVV": {0x2, 0xa, 0x24, 2, false, false},
"VCLMULHVV": {0x2, 0x0, 0x1a, 0, false, false},
"VCLMULHVX": {0x6, 0x0, 0x1a, 0, false, false},
"VCLMULVV": {0x2, 0x0, 0x18, 0, false, false},
"VCLMULVX": {0x6, 0x0, 0x18, 0, false, false},
"VCLZV": {0x2, 0xc, 0x24, 2, false, false},
"VCOMPRESSVM": {0x2, 0x0, 0x2f, 17, false, false},
"VCPOPM": {0x2, 0x10, 0x20, 3, false, false},
"VCPOPV": {0x2, 0xe, 0x24, 2, false, false},
"VCTZV": {0x2, 0xd, 0x24, 2, false, false},
"VDIVUVV": {0x2, 0x0, 0x40, 0, false, false},
"VDIVUVX": {0x6, 0x0, 0x40, 0, false, false},
"VDIVVV": {0x2, 0x0, 0x42, 0, false, false},
"VDIVVX": {0x6, 0x0, 0x42, 0, false, false},
"VFABSV": {0x1, 0x0, 0x14, 16, false, false},
"VFADDVF": {0x5, 0x0, 0x00, 0, false, false},
"VFADDVV": {0x1, 0x0, 0x00, 0, false, false},
"VFCLASSV": {0x1, 0x10, 0x26, 2, false, false},
"VFCVTFXUV": {0x1, 0x2, 0x24, 2, false, false},
"VFCVTFXV": {0x1, 0x3, 0x24, 2, false, false},
"VFCVTRTZXFV": {0x1, 0x7, 0x24, 2, false, false},
"VFCVTRTZXUFV": {0x1, 0x6, 0x24, 2, false, false},
"VFCVTXFV": {0x1, 0x1, 0x24, 2, false, false},
"VFCVTXUFV": {0x1, 0x0, 0x24, 2, false, false},
"VFDIVVF": {0x5, 0x0, 0x40, 0, false, false},
"VFDIVVV": {0x1, 0x0, 0x40, 0, false, false},
"VFIRSTM": {0x2, 0x11, 0x20, 3, false, false},
"VFMACCVF": {0x5, 0x0, 0x58, 1, false, false},
"VFMACCVV": {0x1, 0x0, 0x58, 1, false, false},
"VFMADDVF": {0x5, 0x0, 0x50, 1, false, false},
"VFMADDVV": {0x1, 0x0, 0x50, 1, false, false},
"VFMAXVF": {0x5, 0x0, 0x0c, 0, false, false},
"VFMAXVV": {0x1, 0x0, 0x0c, 0, false, false},
"VFMERGEVFM": {0x5, 0x0, 0x2e, 10, false, false},
"VFMINVF": {0x5, 0x0, 0x08, 0, false, false},
"VFMINVV": {0x1, 0x0, 0x08, 0, false, false},
"VFMSACVF": {0x5, 0x0, 0x5c, 1, false, false},
"VFMSACVV": {0x1, 0x0, 0x5c, 1, false, false},
"VFMSUBVF": {0x5, 0x0, 0x54, 1, false, false},
"VFMSUBVV": {0x1, 0x0, 0x54, 1, false, false},
"VFMULVF": {0x5, 0x0, 0x48, 0, false, false},
"VFMULVV": {0x1, 0x0, 0x48, 0, false, false},
"VFMVFS": {0x1, 0x0, 0x21, 7, false, false},
"VFMVSF": {0x5, 0x0, 0x21, 8, false, false},
"VFMVVF": {0x5, 0x0, 0x2f, 6, false, false},
"VFNCVTFFW": {0x1, 0x14, 0x24, 2, false, false},
"VFNCVTFXUW": {0x1, 0x12, 0x24, 2, false, false},
"VFNCVTFXW": {0x1, 0x13, 0x24, 2, false, false},
"VFNCVTRODFFW": {0x1, 0x15, 0x24, 2, false, false},
"VFNCVTRTZXFW": {0x1, 0x17, 0x24, 2, false, false},
"VFNCVTRTZXUFW": {0x1, 0x16, 0x24, 2, false, false},
"VFNCVTXFW": {0x1, 0x11, 0x24, 2, false, false},
"VFNCVTXUFW": {0x1, 0x10, 0x24, 2, false, false},
"VFNEGV": {0x1, 0x0, 0x12, 16, false, false},
"VFNMACCVF": {0x5, 0x0, 0x5a, 1, false, false},
"VFNMACCVV": {0x1, 0x0, 0x5a, 1, false, false},
"VFNMADDVF": {0x5, 0x0, 0x52, 1, false, false},
"VFNMADDVV": {0x1, 0x0, 0x52, 1, false, false},
"VFNMSACVF": {0x5, 0x0, 0x5e, 1, false, false},
"VFNMSACVV": {0x1, 0x0, 0x5e, 1, false, false},
"VFNMSUBVF": {0x5, 0x0, 0x56, 1, false, false},
"VFNMSUBVV": {0x1, 0x0, 0x56, 1, false, false},
"VFRDIVVF": {0x5, 0x0, 0x42, 0, false, false},
"VFREC7V": {0x1, 0x5, 0x26, 2, false, false},
"VFREDMAXVS": {0x1, 0x0, 0x0e, 0, false, false},
"VFREDMINVS": {0x1, 0x0, 0x0a, 0, false, false},
"VFREDOSUMVS": {0x1, 0x0, 0x06, 0, false, false},
"VFREDUSUMVS": {0x1, 0x0, 0x02, 0, false, false},
"VFRSQRT7V": {0x1, 0x4, 0x26, 2, false, false},
"VFRSUBVF": {0x5, 0x0, 0x4e, 0, false, false},
"VFSGNJNVF": {0x5, 0x0, 0x12, 0, false, false},
"VFSGNJNVV": {0x1, 0x0, 0x12, 0, false, false},
"VFSGNJVF": {0x5, 0x0, 0x10, 0, false, false},
"VFSGNJVV": {0x1, 0x0, 0x10, 0, false, false},
"VFSGNJXVF": {0x5, 0x0, 0x14, 0, false, false},
"VFSGNJXVV": {0x1, 0x0, 0x14, 0, false, false},
"VFSLIDE1DOWNVF": {0x5, 0x0, 0x1e, 0, false, false},
"VFSLIDE1UPVF": {0x5, 0x0, 0x1c, 0, false, false},
"VFSQRTV": {0x1, 0x0, 0x26, 2, false, false},
"VFSUBVF": {0x5, 0x0, 0x04, 0, false, false},
"VFSUBVV": {0x1, 0x0, 0x04, 0, false, false},
"VFWADDVF": {0x5, 0x0, 0x60, 0, false, false},
"VFWADDVV": {0x1, 0x0, 0x60, 0, false, false},
"VFWADDWF": {0x5, 0x0, 0x68, 0, false, false},
"VFWADDWV": {0x1, 0x0, 0x68, 0, false, false},
"VFWCVTFFV": {0x1, 0xc, 0x24, 2, false, false},
"VFWCVTFXUV": {0x1, 0xa, 0x24, 2, false, false},
"VFWCVTFXV": {0x1, 0xb, 0x24, 2, false, false},
"VFWCVTRTZXFV": {0x1, 0xf, 0x24, 2, false, false},
"VFWCVTRTZXUFV": {0x1, 0xe, 0x24, 2, false, false},
"VFWCVTXFV": {0x1, 0x9, 0x24, 2, false, false},
"VFWCVTXUFV": {0x1, 0x8, 0x24, 2, false, false},
"VFWMACCVF": {0x5, 0x0, 0x78, 1, false, false},
"VFWMACCVV": {0x1, 0x0, 0x78, 1, false, false},
"VFWMSACVF": {0x5, 0x0, 0x7c, 1, false, false},
"VFWMSACVV": {0x1, 0x0, 0x7c, 1, false, false},
"VFWMULVF": {0x5, 0x0, 0x70, 0, false, false},
"VFWMULVV": {0x1, 0x0, 0x70, 0, false, false},
"VFWNMACCVF": {0x5, 0x0, 0x7a, 1, false, false},
"VFWNMACCVV": {0x1, 0x0, 0x7a, 1, false, false},
"VFWNMSACVF": {0x5, 0x0, 0x7e, 1, false, false},
"VFWNMSACVV": {0x1, 0x0, 0x7e, 1, false, false},
"VFWREDOSUMVS": {0x1, 0x0, 0x66, 0, false, false},
"VFWREDUSUMVS": {0x1, 0x0, 0x62, 0, false, false},
"VFWSUBVF": {0x5, 0x0, 0x64, 0, false, false},
"VFWSUBVV": {0x1, 0x0, 0x64, 0, false, false},
"VFWSUBWF": {0x5, 0x0, 0x6c, 0, false, false},
"VFWSUBWV": {0x1, 0x0, 0x6c, 0, false, false},
"VIDV": {0x2, 0x11, 0x28, 19, false, false},
"VIOTAM": {0x2, 0x10, 0x28, 3, false, false},
"VMACCVV": {0x2, 0x0, 0x5a, 1, false, false},
"VMACCVX": {0x6, 0x0, 0x5a, 1, false, false},
"VMADCVI": {0x3, 0x0, 0x23, 11, true, false},
"VMADCVIM": {0x3, 0x0, 0x22, 10, true, false},
"VMADCVV": {0x0, 0x0, 0x23, 11, false, false},
"VMADCVVM": {0x0, 0x0, 0x22, 10, false, false},
"VMADCVX": {0x4, 0x0, 0x23, 11, false, false},
"VMADCVXM": {0x4, 0x0, 0x22, 10, false, false},
"VMADDVV": {0x2, 0x0, 0x52, 1, false, false},
"VMADDVX": {0x6, 0x0, 0x52, 1, false, false},
"VMANDMM": {0x2, 0x0, 0x33, 17, false, false},
"VMANDNMM": {0x2, 0x0, 0x31, 17, false, false},
"VMAXUVV": {0x0, 0x0, 0x0c, 0, false, false},
"VMAXUVX": {0x4, 0x0, 0x0c, 0, false, false},
"VMAXVV": {0x0, 0x0, 0x0e, 0, false, false},
"VMAXVX": {0x4, 0x0, 0x0e, 0, false, false},
"VMCLRM": {0x2, 0x0, 0x37, 18, false, false},
"VMERGEVIM": {0x3, 0x0, 0x2e, 10, true, false},
"VMERGEVVM": {0x0, 0x0, 0x2e, 10, false, false},
"VMERGEVXM": {0x4, 0x0, 0x2e, 10, false, false},
"VMFEQVF": {0x5, 0x0, 0x30, 0, false, false},
"VMFEQVV": {0x1, 0x0, 0x30, 0, false, false},
"VMFGEVF": {0x5, 0x0, 0x3e, 0, false, false},
"VMFGEVV": {0x1, 0x0, 0x32, 14, false, false},
"VMFGTVF": {0x5, 0x0, 0x3a, 0, false, false},
"VMFGTVV": {0x1, 0x0, 0x36, 14, false, false},
"VMFLEVF": {0x5, 0x0, 0x32, 0, false, false},
"VMFLEVV": {0x1, 0x0, 0x32, 0, false, false},
"VMFLTVF": {0x5, 0x0, 0x36, 0, false, false},
"VMFLTVV": {0x1, 0x0, 0x36, 0, false, false},
"VMFNEVF": {0x5, 0x0, 0x38, 0, false, false},
"VMFNEVV": {0x1, 0x0, 0x38, 0, false, false},
"VMINUVV": {0x0, 0x0, 0x08, 0, false, false},
"VMINUVX": {0x4, 0x0, 0x08, 0, false, false},
"VMINVV": {0x0, 0x0, 0x0a, 0, false, false},
"VMINVX": {0x4, 0x0, 0x0a, 0, false, false},
"VMMVM": {0x2, 0x0, 0x33, 17, false, false},
"VMNANDMM": {0x2, 0x0, 0x3b, 17, false, false},
"VMNORMM": {0x2, 0x0, 0x3d, 17, false, false},
"VMNOTM": {0x2, 0x0, 0x3b, 17, false, false},
"VMORMM": {0x2, 0x0, 0x35, 17, false, false},
"VMORNMM": {0x2, 0x0, 0x39, 17, false, false},
"VMSBCVV": {0x0, 0x0, 0x27, 11, false, false},
"VMSBCVVM": {0x0, 0x0, 0x26, 10, false, false},
"VMSBCVX": {0x4, 0x0, 0x27, 11, false, false},
"VMSBCVXM": {0x4, 0x0, 0x26, 10, false, false},
"VMSBFM": {0x2, 0x1, 0x28, 3, false, false},
"VMSEQVI": {0x3, 0x0, 0x30, 0, true, false},
"VMSEQVV": {0x0, 0x0, 0x30, 0, false, false},
"VMSEQVX": {0x4, 0x0, 0x30, 0, false, false},
"VMSETM": {0x2, 0x0, 0x3f, 18, false, false},
"VMSGEUVI": {0x3, 0x0, 0x3c, 15, true, false},
"VMSGEUVV": {0x0, 0x0, 0x38, 14, false, false},
"VMSGEVI": {0x3, 0x0, 0x3e, 15, true, false},
"VMSGEVV": {0x0, 0x0, 0x3a, 14, false, false},
"VMSGTUVI": {0x3, 0x0, 0x3c, 0, true, false},
"VMSGTUVV": {0x0, 0x0, 0x34, 14, false, false},
"VMSGTUVX": {0x4, 0x0, 0x3c, 0, false, false},
"VMSGTVI": {0x3, 0x0, 0x3e, 0, true, false},
"VMSGTVV": {0x0, 0x0, 0x36, 14, false, false},
"VMSGTVX": {0x4, 0x0, 0x3e, 0, false, false},
"VMSIFM": {0x2, 0x3, 0x28, 3, false, false},
"VMSLEUVI": {0x3, 0x0, 0x38, 0, true, false},
"VMSLEUVV": {0x0, 0x0, 0x38, 0, false, false},
"VMSLEUVX": {0x4, 0x0, 0x38, 0, false, false},
"VMSLEVI": {0x3, 0x0, 0x3a, 0, true, false},
"VMSLEVV": {0x0, 0x0, 0x3a, 0, false, false},
"VMSLEVX": {0x4, 0x0, 0x3a, 0, false, false},
"VMSLTUVI": {0x3, 0x0, 0x38, 15, true, false},
"VMSLTUVV": {0x0, 0x0, 0x34, 0, false, false},
"VMSLTUVX": {0x4, 0x0, 0x34, 0, false, false},
"VMSLTVI": {0x3, 0x0, 0x3a, 15, true, false},
"VMSLTVV": {0x0, 0x0, 0x36, 0, false, false},
"VMSLTVX": {0x4, 0x0, 0x36, 0, false, false},
"VMSNEVI": {0x3, 0x0, 0x32, 0, true, false},
"VMSNEVV": {0x0, 0x0, 0x32, 0, false, false},
"VMSNEVX": {0x4, 0x0, 0x32, 0, false, false},
"VMSOFM": {0x2, 0x2, 0x28, 3, false, false},
"VMULHSUVV": {0x2, 0x0, 0x4c, 0, false, false},
"VMULHSUVX": {0x6, 0x0, 0x4c, 0, false, false},
"VMULHUVV": {0x2, 0x0, 0x48, 0, false, false},
"VMULHUVX": {0x6, 0x0, 0x48, 0, false, false},
"VMULHVV": {0x2, 0x0, 0x4e, 0, false, false},
"VMULHVX": {0x6, 0x0, 0x4e, 0, false, false},
"VMULVV": {0x2, 0x0, 0x4a, 0, false, false},
"VMULVX": {0x6, 0x0, 0x4a, 0, false, false},
"VMV1RV": {0x3, 0x0, 0x4f, 7, false, false},
"VMV2RV": {0x3, 0x1, 0x4f, 7, false, false},
"VMV4RV": {0x3, 0x3, 0x4f, 7, false, false},
"VMV8RV": {0x3, 0x7, 0x4f, 7, false, false},
"VMVSX": {0x6, 0x0, 0x21, 8, false, false},
"VMVVI": {0x3, 0x0, 0x2f, 5, true, false},
"VMVVV": {0x0, 0x0, 0x2f, 4, false, false},
"VMVVX": {0x4, 0x0, 0x2f, 4, false, false},
"VMVXS": {0x2, 0x0, 0x21, 7, false, false},
"VMXNORMM": {0x2, 0x0, 0x3f, 17, false, false},
"VMXORMM": {0x2, 0x0, 0x37, 17, false, false},
"VNCLIPUWI": {0x3, 0x0, 0x5c, 0, true, true},
"VNCLIPUWV": {0x0, 0x0, 0x5c, 0, false, false},
"VNCLIPUWX": {0x4, 0x0, 0x5c, 0, false, false},
"VNCLIPWI": {0x3, 0x0, 0x5e, 0, true, true},
"VNCLIPWV": {0x0, 0x0, 0x5e, 0, false, false},
"VNCLIPWX": {0x4, 0x0, 0x5e, 0, false, false},
"VNCVTXXW": {0x4, 0x0, 0x58, 12, false, false},
"VNEGV": {0x4, 0x0, 0x06, 12, false, false},
"VNMSACVV": {0x2, 0x0, 0x5e, 1, false, false},
"VNMSACVX": {0x6, 0x0, 0x5e, 1, false, false},
"VNMSUBVV": {0x2, 0x0, 0x56, 1, false, false},
"VNMSUBVX": {0x6, 0x0, 0x56, 1, false, false},
"VNOTV": {0x3, 0x0, 0x16, 13, true, false},
"VNSRAWI": {0x3, 0x0, 0x5a, 0, true, true},
"VNSRAWV": {0x0, 0x0, 0x5a, 0, false, false},
"VNSRAWX": {0x4, 0x0, 0x5a, 0, false, false},
"VNSRLWI": {0x3, 0x0, 0x58, 0, true, true},
"VNSRLWV": {0x0, 0x0, 0x58, 0, false, false},
"VNSRLWX": {0x4, 0x0, 0x58, 0, false, false},
"VORVI": {0x3, 0x0, 0x14, 0, true, false},
"VORVV": {0x0, 0x0, 0x14, 0, false, false},
"VORVX": {0x4, 0x0, 0x14, 0, false, false},
"VREDANDVS": {0x2, 0x0, 0x02, 0, false, false},
"VREDMAXUVS": {0x2, 0x0, 0x0c, 0, false, false},
"VREDMAXVS": {0x2, 0x0, 0x0e, 0, false, false},
"VREDMINUVS": {0x2, 0x0, 0x08, 0, false, false},
"VREDMINVS": {0x2, 0x0, 0x0a, 0, false, false},
"VREDORVS": {0x2, 0x0, 0x04, 0, false, false},
"VREDSUMVS": {0x2, 0x0, 0x00, 0, false, false},
"VREDXORVS": {0x2, 0x0, 0x06, 0, false, false},
"VREMUVV": {0x2, 0x0, 0x44, 0, false, false},
"VREMUVX": {0x6, 0x0, 0x44, 0, false, false},
"VREMVV": {0x2, 0x0, 0x46, 0, false, false},
"VREMVX": {0x6, 0x0, 0x46, 0, false, false},
"VREV8V": {0x2, 0x9, 0x24, 2, false, false},
"VRGATHEREI16VV": {0x0, 0x0, 0x1c, 0, false, false},
"VRGATHERVI": {0x3, 0x0, 0x18, 0, true, true},
"VRGATHERVV": {0x0, 0x0, 0x18, 0, false, false},
"VRGATHERVX": {0x4, 0x0, 0x18, 0, false, false},
"VROLVV": {0x0, 0x0, 0x2a, 0, false, false},
"VROLVX": {0x4, 0x0, 0x2a, 0, false, false},
"VRORVI": {0x3, 0x0, 0x28, 0, true, true},
"VRORVV": {0x0, 0x0, 0x28, 0, false, false},
"VRORVX": {0x4, 0x0, 0x28, 0, false, false},
"VRSUBVI": {0x3, 0x0, 0x06, 0, true, false},
"VRSUBVX": {0x4, 0x0, 0x06, 0, false, false},
"VSADDUVI": {0x3, 0x0, 0x40, 0, true, false},
"VSADDUVV": {0x0, 0x0, 0x40, 0, false, false},
"VSADDUVX": {0x4, 0x0, 0x40, 0, false, false},
"VSADDVI": {0x3, 0x0, 0x42, 0, true, false},
"VSADDVV": {0x0, 0x0, 0x42, 0, false, false},
"VSADDVX": {0x4, 0x0, 0x42, 0, false, false},
"VSBCVVM": {0x0, 0x0, 0x24, 9, false, false},
"VSBCVXM": {0x4, 0x0, 0x24, 9, false, false},
"VSEXTVF2": {0x2, 0x7, 0x24, 2, false, false},
"VSEXTVF4": {0x2, 0x5, 0x24, 2, false, false},
"VSEXTVF8": {0x2, 0x3, 0x24, 2, false, false},
"VSLIDE1DOWNVX": {0x6, 0x0, 0x1e, 0, false, false},
"VSLIDE1UPVX": {0x6, 0x0, 0x1c, 0, false, false},
"VSLIDEDOWNVI": {0x3, 0x0, 0x1e, 0, true, true},
"VSLIDEDOWNVX": {0x4, 0x0, 0x1e, 0, false, false},
"VSLIDEUPVI": {0x3, 0x0, 0x1c, 0, true, true},
"VSLIDEUPVX": {0x4, 0x0, 0x1c, 0, false, false},
"VSLLVI": {0x3, 0x0, 0x4a, 0, true, true},
"VSLLVV": {0x0, 0x0, 0x4a, 0, false, false},
"VSLLVX": {0x4, 0x0, 0x4a, 0, false, false},
"VSMULVV": {0x0, 0x0, 0x4e, 0, false, false},
"VSMULVX": {0x4, 0x0, 0x4e, 0, false, false},
"VSRAVI": {0x3, 0x0, 0x52, 0, true, true},
"VSRAVV": {0x0, 0x0, 0x52, 0, false, false},
"VSRAVX": {0x4, 0x0, 0x52, 0, false, false},
"VSRLVI": {0x3, 0x0, 0x50, 0, true, true},
"VSRLVV": {0x0, 0x0, 0x50, 0, false, false},
"VSRLVX": {0x4, 0x0, 0x50, 0, false, false},
"VSSRAVI": {0x3, 0x0, 0x56, 0, true, true},
"VSSRAVV": {0x0, 0x0, 0x56, 0, false, false},
"VSSRAVX": {0x4, 0x0, 0x56, 0, false, false},
"VSSRLVI": {0x3, 0x0, 0x54, 0, true, true},
"VSSRLVV": {0x0, 0x0, 0x54, 0, false, false},
"VSSRLVX": {0x4, 0x0, 0x54, 0, false, false},
"VSSUBUVV": {0x0, 0x0, 0x44, 0, false, false},
"VSSUBUVX": {0x4, 0x0, 0x44, 0, false, false},
"VSSUBVV": {0x0, 0x0, 0x46, 0, false, false},
"VSSUBVX": {0x4, 0x0, 0x46, 0, false, false},
"VSUBVV": {0x0, 0x0, 0x04, 0, false, false},
"VSUBVX": {0x4, 0x0, 0x04, 0, false, false},
"VWADDUVV": {0x2, 0x0, 0x60, 0, false, false},
"VWADDUVX": {0x6, 0x0, 0x60, 0, false, false},
"VWADDUWV": {0x2, 0x0, 0x68, 0, false, false},
"VWADDUWX": {0x6, 0x0, 0x68, 0, false, false},
"VWADDVV": {0x2, 0x0, 0x62, 0, false, false},
"VWADDVX": {0x6, 0x0, 0x62, 0, false, false},
"VWADDWV": {0x2, 0x0, 0x6a, 0, false, false},
"VWADDWX": {0x6, 0x0, 0x6a, 0, false, false},
"VWCVTUXXV": {0x6, 0x0, 0x60, 12, false, false},
"VWCVTXXV": {0x6, 0x0, 0x62, 12, false, false},
"VWMACCSUVV": {0x2, 0x0, 0x7e, 1, false, false},
"VWMACCSUVX": {0x6, 0x0, 0x7e, 1, false, false},
"VWMACCUSVX": {0x6, 0x0, 0x7c, 1, false, false},
"VWMACCUVV": {0x2, 0x0, 0x78, 1, false, false},
"VWMACCUVX": {0x6, 0x0, 0x78, 1, false, false},
"VWMACCVV": {0x2, 0x0, 0x7a, 1, false, false},
"VWMACCVX": {0x6, 0x0, 0x7a, 1, false, false},
"VWMULSUVV": {0x2, 0x0, 0x74, 0, false, false},
"VWMULSUVX": {0x6, 0x0, 0x74, 0, false, false},
"VWMULUVV": {0x2, 0x0, 0x70, 0, false, false},
"VWMULUVX": {0x6, 0x0, 0x70, 0, false, false},
"VWMULVV": {0x2, 0x0, 0x76, 0, false, false},
"VWMULVX": {0x6, 0x0, 0x76, 0, false, false},
"VWREDSUMUVS": {0x0, 0x0, 0x60, 0, false, false},
"VWREDSUMVS": {0x0, 0x0, 0x62, 0, false, false},
"VWSLLVI": {0x3, 0x0, 0x6a, 0, true, true},
"VWSLLVV": {0x0, 0x0, 0x6a, 0, false, false},
"VWSLLVX": {0x4, 0x0, 0x6a, 0, false, false},
"VWSUBUVV": {0x2, 0x0, 0x64, 0, false, false},
"VWSUBUVX": {0x6, 0x0, 0x64, 0, false, false},
"VWSUBUWV": {0x2, 0x0, 0x6c, 0, false, false},
"VWSUBUWX": {0x6, 0x0, 0x6c, 0, false, false},
"VWSUBVV": {0x2, 0x0, 0x66, 0, false, false},
"VWSUBVX": {0x6, 0x0, 0x66, 0, false, false},
"VWSUBWV": {0x2, 0x0, 0x6e, 0, false, false},
"VWSUBWX": {0x6, 0x0, 0x6e, 0, false, false},
"VXORVI": {0x3, 0x0, 0x16, 0, true, false},
"VXORVV": {0x0, 0x0, 0x16, 0, false, false},
"VXORVX": {0x4, 0x0, 0x16, 0, false, false},
"VZEXTVF2": {0x2, 0x6, 0x24, 2, false, false},
"VZEXTVF4": {0x2, 0x4, 0x24, 2, false, false},
"VZEXTVF8": {0x2, 0x2, 0x24, 2, false, false},
}
// ---- RVC (compressed) encoding helpers ----
// isRVCIntReg reports whether a register number can be encoded in the 3-bit