fix(riscv64): compressed store offsets, FENCE and branch range checks

Assisted-by: GLM 5.3

testdata/verify/rvcstore_riscv64.s

@@ -0,0 +1,48 @@
+// Copyright (c) 2026 Petr Balvín <opensource@petrbalvin.org> (https://petrbalvin.org)
+// SPDX-License-Identifier: BSD-3-Clause
+
+// rvcstore exercises the register-relative compressed stores with offsets
+// that set immediate bits 4 and 5, the bare FENCE, and the GOROOT width
+// spellings of the loads and stores, byte-parity-checked against go tool asm.
+
+#include "textflag.h"
+
+TEXT ·stores(SB), NOSPLIT, $0
+	SD  X9, 24(X8)
+	SW  X10, 16(X11)
+	FSD F8, 40(X12)
+	LD  24(X8), X9
+	LW  16(X11), X10
+	FLD 40(X12), F8
+	RET
+
+TEXT ·fence(SB), NOSPLIT, $0
+	FENCE
+	ECALL
+	RET
+
+// The GOROOT width spellings: MOVW lowers to LW/SW and compresses exactly
+// like the base mnemonic, the byte/half and unsigned forms stay wide.
+TEXT ·argwidths(SB), NOSPLIT, $0-24
+	MOVW  x+0(FP), X9
+	MOVW  X9, y+4(FP)
+	MOVWU z+8(FP), X10
+	MOVB  b+12(FP), X11
+	MOVBU c+13(FP), X12
+	MOVH  h+16(FP), X13
+	MOVHU u+18(FP), X14
+	RET
+
+TEXT ·spwidths(SB), NOSPLIT, $32-0
+	MOVW 4(SP), X9
+	MOVW X9, 8(SP)
+	MOV  16(SP), X10
+	MOV  X10, 24(SP)
+	RET
+
+TEXT ·fpwidths(SB), NOSPLIT, $0-16
+	MOVD d+0(FP), F8
+	MOVD F8, r+8(FP)
+	MOVW w+0(FP), X9
+	MOVW X9, v+4(FP)
+	RET