feat(arch): add the AVX512-FP16 FMA families to the extension layer
Assisted-by: GLM 5.3 Flash
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petrbalvin committed
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@@ -1100,6 +1100,219 @@ var amd64GoldenRows = []amd64GoldenRow{
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{"vrndscaleph k7 zeroing", "VRNDSCALEPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtZmm(5), ExtWriteMasked(ExtZmm(6), 7, true)},
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"62f37ccf08f57b", "62 f3 7c cf 08 f5 7b vrndscaleph $0x7b,%zmm5,%zmm6{%k7}{z}"},
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// The AVX512-FP16 packed fused multiply-add, twelve mnemonics by three
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// lengths: the 512-bit rows on the suite's high registers, the VL rows
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// on the low ones, every register form quoted from the local GNU
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// assembler's output (EVEX.NDS.66.MAP6.W0 throughout).
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{"vfmadd132ph", "VFMADD132PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
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"6206154098f4", "62 06 15 40 98 f4 vfmadd132ph %zmm28,%zmm29,%zmm30"},
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{"vfmadd213ph", "VFMADD213PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
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"62061540a8f4", "62 06 15 40 a8 f4 vfmadd213ph %zmm28,%zmm29,%zmm30"},
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{"vfmadd231ph", "VFMADD231PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
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"62061540b8f4", "62 06 15 40 b8 f4 vfmadd231ph %zmm28,%zmm29,%zmm30"},
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{"vfmsub132ph", "VFMSUB132PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
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"620615409af4", "62 06 15 40 9a f4 vfmsub132ph %zmm28,%zmm29,%zmm30"},
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{"vfmsub213ph", "VFMSUB213PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
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"62061540aaf4", "62 06 15 40 aa f4 vfmsub213ph %zmm28,%zmm29,%zmm30"},
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{"vfmsub231ph", "VFMSUB231PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
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"62061540baf4", "62 06 15 40 ba f4 vfmsub231ph %zmm28,%zmm29,%zmm30"},
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{"vfmaddsub132ph", "VFMADDSUB132PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
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"6206154096f4", "62 06 15 40 96 f4 vfmaddsub132ph %zmm28,%zmm29,%zmm30"},
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{"vfmaddsub213ph", "VFMADDSUB213PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
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"62061540a6f4", "62 06 15 40 a6 f4 vfmaddsub213ph %zmm28,%zmm29,%zmm30"},
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{"vfmaddsub231ph", "VFMADDSUB231PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
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"62061540b6f4", "62 06 15 40 b6 f4 vfmaddsub231ph %zmm28,%zmm29,%zmm30"},
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{"vfmsubadd132ph", "VFMSUBADD132PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
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"6206154097f4", "62 06 15 40 97 f4 vfmsubadd132ph %zmm28,%zmm29,%zmm30"},
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{"vfmsubadd213ph", "VFMSUBADD213PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
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"62061540a7f4", "62 06 15 40 a7 f4 vfmsubadd213ph %zmm28,%zmm29,%zmm30"},
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{"vfmsubadd231ph", "VFMSUBADD231PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtZmm(30)},
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"62061540b7f4", "62 06 15 40 b7 f4 vfmsubadd231ph %zmm28,%zmm29,%zmm30"},
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{"vfmadd132ph ymm", "VFMADD132PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f6552898f4", "62 f6 55 28 98 f4 vfmadd132ph %ymm4,%ymm5,%ymm6"},
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{"vfmadd132ph xmm", "VFMADD132PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f6550898f4", "62 f6 55 08 98 f4 vfmadd132ph %xmm4,%xmm5,%xmm6"},
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{"vfmadd213ph ymm", "VFMADD213PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f65528a8f4", "62 f6 55 28 a8 f4 vfmadd213ph %ymm4,%ymm5,%ymm6"},
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{"vfmadd213ph xmm", "VFMADD213PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f65508a8f4", "62 f6 55 08 a8 f4 vfmadd213ph %xmm4,%xmm5,%xmm6"},
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{"vfmadd231ph ymm", "VFMADD231PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f65528b8f4", "62 f6 55 28 b8 f4 vfmadd231ph %ymm4,%ymm5,%ymm6"},
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{"vfmadd231ph xmm", "VFMADD231PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f65508b8f4", "62 f6 55 08 b8 f4 vfmadd231ph %xmm4,%xmm5,%xmm6"},
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{"vfmsub132ph ymm", "VFMSUB132PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f655289af4", "62 f6 55 28 9a f4 vfmsub132ph %ymm4,%ymm5,%ymm6"},
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{"vfmsub132ph xmm", "VFMSUB132PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f655089af4", "62 f6 55 08 9a f4 vfmsub132ph %xmm4,%xmm5,%xmm6"},
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{"vfmsub213ph ymm", "VFMSUB213PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f65528aaf4", "62 f6 55 28 aa f4 vfmsub213ph %ymm4,%ymm5,%ymm6"},
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{"vfmsub213ph xmm", "VFMSUB213PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f65508aaf4", "62 f6 55 08 aa f4 vfmsub213ph %xmm4,%xmm5,%xmm6"},
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{"vfmsub231ph ymm", "VFMSUB231PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f65528baf4", "62 f6 55 28 ba f4 vfmsub231ph %ymm4,%ymm5,%ymm6"},
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{"vfmsub231ph xmm", "VFMSUB231PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f65508baf4", "62 f6 55 08 ba f4 vfmsub231ph %xmm4,%xmm5,%xmm6"},
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{"vfmaddsub132ph ymm", "VFMADDSUB132PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f6552896f4", "62 f6 55 28 96 f4 vfmaddsub132ph %ymm4,%ymm5,%ymm6"},
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{"vfmaddsub132ph xmm", "VFMADDSUB132PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f6550896f4", "62 f6 55 08 96 f4 vfmaddsub132ph %xmm4,%xmm5,%xmm6"},
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{"vfmaddsub213ph ymm", "VFMADDSUB213PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f65528a6f4", "62 f6 55 28 a6 f4 vfmaddsub213ph %ymm4,%ymm5,%ymm6"},
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{"vfmaddsub213ph xmm", "VFMADDSUB213PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f65508a6f4", "62 f6 55 08 a6 f4 vfmaddsub213ph %xmm4,%xmm5,%xmm6"},
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{"vfmaddsub231ph ymm", "VFMADDSUB231PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f65528b6f4", "62 f6 55 28 b6 f4 vfmaddsub231ph %ymm4,%ymm5,%ymm6"},
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{"vfmaddsub231ph xmm", "VFMADDSUB231PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f65508b6f4", "62 f6 55 08 b6 f4 vfmaddsub231ph %xmm4,%xmm5,%xmm6"},
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{"vfmsubadd132ph ymm", "VFMSUBADD132PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f6552897f4", "62 f6 55 28 97 f4 vfmsubadd132ph %ymm4,%ymm5,%ymm6"},
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{"vfmsubadd132ph xmm", "VFMSUBADD132PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f6550897f4", "62 f6 55 08 97 f4 vfmsubadd132ph %xmm4,%xmm5,%xmm6"},
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{"vfmsubadd213ph ymm", "VFMSUBADD213PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f65528a7f4", "62 f6 55 28 a7 f4 vfmsubadd213ph %ymm4,%ymm5,%ymm6"},
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{"vfmsubadd213ph xmm", "VFMSUBADD213PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f65508a7f4", "62 f6 55 08 a7 f4 vfmsubadd213ph %xmm4,%xmm5,%xmm6"},
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{"vfmsubadd231ph ymm", "VFMSUBADD231PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtYmm(6)},
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"62f65528b7f4", "62 f6 55 28 b7 f4 vfmsubadd231ph %ymm4,%ymm5,%ymm6"},
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{"vfmsubadd231ph xmm", "VFMSUBADD231PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtXmm(6)},
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"62f65508b7f4", "62 f6 55 08 b7 f4 vfmsubadd231ph %xmm4,%xmm5,%xmm6"},
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// The scalar fused multiply-add, EVEX.NDS.LIG.66.MAP6.W0: the add
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// opcodes one above the packed ones, the subtract two above them.
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{"vfmadd132sh", "VFMADD132SH",
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[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtXmm(30)},
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"6206150099f4", "62 06 15 00 99 f4 vfmadd132sh %xmm28,%xmm29,%xmm30"},
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{"vfmadd213sh", "VFMADD213SH",
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[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtXmm(30)},
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"62061500a9f4", "62 06 15 00 a9 f4 vfmadd213sh %xmm28,%xmm29,%xmm30"},
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{"vfmadd231sh", "VFMADD231SH",
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[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtXmm(30)},
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"62061500b9f4", "62 06 15 00 b9 f4 vfmadd231sh %xmm28,%xmm29,%xmm30"},
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{"vfmsub132sh", "VFMSUB132SH",
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[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtXmm(30)},
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"620615009bf4", "62 06 15 00 9b f4 vfmsub132sh %xmm28,%xmm29,%xmm30"},
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{"vfmsub213sh", "VFMSUB213SH",
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[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtXmm(30)},
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"62061500abf4", "62 06 15 00 ab f4 vfmsub213sh %xmm28,%xmm29,%xmm30"},
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{"vfmsub231sh", "VFMSUB231SH",
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[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtXmm(30)},
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"62061500bbf4", "62 06 15 00 bb f4 vfmsub231sh %xmm28,%xmm29,%xmm30"},
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// The FMA memory forms: the second source reads m512, m256, m128 or the
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// scalar m16 from memory. The disp8 rows quote the listing's compressed
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// spellings, whose source is N times the plain displacement the bytes
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// carry; the R12 row exercises the SIB byte.
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{"vfmadd132ph memory source", "VFMADD132PH",
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[]ExtOperand{ExtZmm(29), ExtMemory(1, 127), ExtZmm(30)},
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"6266154098717f", "62 66 15 40 98 71 7f vfmadd132ph 0x1fc0(%rcx),%zmm29,%zmm30 (Disp8(7f))"},
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{"vfmadd132ph ymm memory source", "VFMADD132PH",
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[]ExtOperand{ExtYmm(5), ExtMemory(1, 127), ExtYmm(6)},
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"62f6552898717f", "62 f6 55 28 98 71 7f vfmadd132ph 0xfe0(%ecx),%ymm5,%ymm6 (Disp8(7f))"},
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{"vfmadd132ph xmm memory source", "VFMADD132PH",
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[]ExtOperand{ExtXmm(5), ExtMemory(1, 127), ExtXmm(6)},
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"62f6550898717f", "62 f6 55 08 98 71 7f vfmadd132ph 0x7f0(%ecx),%xmm5,%xmm6 (Disp8(7f))"},
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{"vfmadd132ph memory source", "VFMADD132PH",
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[]ExtOperand{ExtZmm(29), ExtMemory(9, 0), ExtZmm(30)},
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"624615409831", "62 46 15 40 98 31 vfmadd132ph (%r9),%zmm29,%zmm30"},
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{"vfmsub231ph memory source", "VFMSUB231PH",
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[]ExtOperand{ExtZmm(29), ExtMemory(9, 0), ExtZmm(30)},
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"62461540ba31", "62 46 15 40 ba 31 vfmsub231ph (%r9),%zmm29,%zmm30"},
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{"vfmaddsub132ph memory source over an R12 base", "VFMADDSUB132PH",
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[]ExtOperand{ExtZmm(29), ExtMemory(12, 0), ExtZmm(30)},
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"62461540963424", ""},
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{"vfmadd132sh memory source", "VFMADD132SH",
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[]ExtOperand{ExtXmm(29), ExtMemory(9, 0), ExtXmm(30)},
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"624615009931", "62 46 15 00 99 31 vfmadd132sh (%r9),%xmm29,%xmm30"},
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{"vfmadd132sh memory source disp8", "VFMADD132SH",
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[]ExtOperand{ExtXmm(29), ExtMemory(1, 1), ExtXmm(30)},
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"62661500997101", "62 66 15 00 99 71 01 vfmadd132sh 0x2(%rcx),%xmm29,%xmm30 (Disp8(01))"},
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{"vfmsub132sh memory source", "VFMSUB132SH",
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[]ExtOperand{ExtXmm(29), ExtMemory(9, 0), ExtXmm(30)},
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"624615009b31", "62 46 15 00 9b 31 vfmsub132sh (%r9),%xmm29,%xmm30"},
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// The FMA broadcast forms: one half-precision element the hardware
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// splats across the lanes, {1to32}, {1to16} and {1to8}.
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{"vfmadd132ph broadcast source", "VFMADD132PH",
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[]ExtOperand{ExtZmm(29), ExtBroadcast(9, 0), ExtZmm(30)},
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"624615509831", "62 46 15 50 98 31 vfmadd132ph (%r9){1to32},%zmm29,%zmm30"},
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{"vfmadd132ph ymm broadcast source", "VFMADD132PH",
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[]ExtOperand{ExtYmm(5), ExtBroadcast(1, 0), ExtYmm(6)},
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"62f655389831", "62 f6 55 38 98 31 vfmadd132ph (%ecx){1to16},%ymm5,%ymm6"},
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{"vfmadd132ph xmm broadcast source", "VFMADD132PH",
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[]ExtOperand{ExtXmm(5), ExtBroadcast(1, 0), ExtXmm(6)},
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"62f655189831", "62 f6 55 18 98 31 vfmadd132ph (%ecx){1to8},%xmm5,%xmm6"},
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{"vfmaddsub132ph broadcast source", "VFMADDSUB132PH",
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[]ExtOperand{ExtZmm(29), ExtBroadcast(9, 0), ExtZmm(30)},
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"624615509631", "62 46 15 50 96 31 vfmaddsub132ph (%r9){1to32},%zmm29,%zmm30"},
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{"vfmsubadd231ph broadcast source", "VFMSUBADD231PH",
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[]ExtOperand{ExtZmm(29), ExtBroadcast(9, 0), ExtZmm(30)},
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"62461550b731", "62 46 15 50 b7 31 vfmsubadd231ph (%r9){1to32},%zmm29,%zmm30"},
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// The FMA rounding rows: the 512-bit register forms take EVEX.RC, the
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// scalar register forms beside them.
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{"vfmadd132ph rz-sae", "VFMADD132PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtRounded(ExtZmm(30), ExtRoundTruncate)},
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"6206157098f4", "62 06 15 70 98 f4 vfmadd132ph {rz-sae},%zmm28,%zmm29,%zmm30"},
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{"vfmadd213ph rn-sae", "VFMADD213PH",
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[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundNearest)},
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"62f65518a8f4", "62 f6 55 18 a8 f4 vfmadd213ph {rn-sae},%zmm4,%zmm5,%zmm6"},
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{"vfmsub132ph ru-sae", "VFMSUB132PH",
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[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundUp)},
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"62f655589af4", "62 f6 55 58 9a f4 vfmsub132ph {ru-sae},%zmm4,%zmm5,%zmm6"},
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{"vfmaddsub231ph rd-sae", "VFMADDSUB231PH",
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[]ExtOperand{ExtZmm(5), ExtZmm(4), ExtRounded(ExtZmm(6), ExtRoundDown)},
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"62f65538b6f4", "62 f6 55 38 b6 f4 vfmaddsub231ph {rd-sae},%zmm4,%zmm5,%zmm6"},
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{"vfmadd132sh rn-sae", "VFMADD132SH",
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[]ExtOperand{ExtXmm(5), ExtXmm(4), ExtRounded(ExtXmm(6), ExtRoundNearest)},
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"62f6551899f4", "62 f6 55 18 99 f4 vfmadd132sh {rn-sae},%xmm4,%xmm5,%xmm6"},
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{"vfmadd231sh rz-sae, high registers", "VFMADD231SH",
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[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtRounded(ExtXmm(30), ExtRoundTruncate)},
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"62061570b9f4", "62 06 15 70 b9 f4 vfmadd231sh {rz-sae},%xmm28,%xmm29,%xmm30"},
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// The FMA write masks over the packed destinations.
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{"vfmadd132ph k7 zeroing", "VFMADD132PH",
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[]ExtOperand{ExtZmm(29), ExtZmm(28), ExtWriteMasked(ExtZmm(30), 7, true)},
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"620615c798f4", "62 06 15 c7 98 f4 vfmadd132ph %zmm28,%zmm29,%zmm30{%k7}{z}"},
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{"vfmaddsub132ph k5 merging, memory source", "VFMADDSUB132PH",
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[]ExtOperand{ExtZmm(29), ExtMemory(9, 0), ExtWriteMasked(ExtZmm(30), 5, false)},
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"624615459631", "62 46 15 45 96 31 vfmaddsub132ph (%r9),%zmm29,%zmm30{%k5}"},
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}
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// amd64ResolveEntry finds the table entry a golden row exercises: the entry
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@@ -1375,7 +1588,7 @@ func TestAmd64ExtRejects(t *testing.T) {
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"the position takes none"},
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{"write mask on the control form's destination", "VGETMANTSH",
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[]ExtOperand{ExtImmediate(0x0b), ExtXmm(29), ExtXmm(28), ExtWriteMasked(ExtXmm(30), 7, true)},
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"the position takes none"},
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"the entry's destination takes none"},
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{"write mask where the destination is memory", "VCOMISH",
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[]ExtOperand{ExtXmm(30), ExtOperand{Kind: ExtMem, Reg: 9, HasMask: true, Mask: 2}},
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"the entry's destination takes none"},
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@@ -1430,6 +1643,15 @@ func TestAmd64ExtRejects(t *testing.T) {
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{"reserved upper nibble on the packed mantissa control", "VGETMANTPH",
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[]ExtOperand{ExtImmediate(0x7b), ExtZmm(5), ExtZmm(6)},
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"reserved and must be zero"},
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{"broadcast on the scalar multiply-add", "VFMADD132SH",
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[]ExtOperand{ExtXmm(29), ExtBroadcast(9, 0), ExtXmm(30)},
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"the entry's memory operand takes none"},
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{"rounding on the 256-bit multiply-add", "VFMADD132PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(4), ExtRounded(ExtYmm(6), ExtRoundNearest)},
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"the entry's destination takes none"},
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{"a register where the multiply-add reads memory", "VFMSUB231PH",
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[]ExtOperand{ExtZmm(29), ExtYmm(4), ExtZmm(30)},
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"wants a ZMM register"},
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} {
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in := amd64ExtInstr(t, tt.mnem, operandClass(t, tt.ops))
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_, err := in.Encode(tt.ops)
|
||||
@@ -1574,7 +1796,7 @@ func TestAmd64ExtArchBinding(t *testing.T) {
|
||||
t.Errorf("Extensions(%s) carries %d instructions, want none", a, len(got))
|
||||
}
|
||||
}
|
||||
if got := Extensions(AMD64); len(got) != 121 {
|
||||
t.Errorf("the amd64 layer registers %d instructions, want 121", len(got))
|
||||
if got := Extensions(AMD64); len(got) != 163 {
|
||||
t.Errorf("the amd64 layer registers %d instructions, want 163", len(got))
|
||||
}
|
||||
}
|
||||
Reference in new issue
Block a user