Assisted-by: GLM 5.3 Flash
This commit is contained in:
+221
-7
@@ -61,6 +61,21 @@ const (
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// vexImmRMGPR is the immediate form over general-purpose registers
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// (RORX): reg = dst, rm = src, imm8 = op0, L = 0.
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vexImmRMGPR
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// vexRMOpGPR is the two-operand /digit form over general-purpose
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// registers (BLSI, BLSMSK, BLSR): ModRM.reg = /digit, ModRM.rm = src
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// (op0), VEX.vvvv = dst (op1), L = 0.
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vexRMOpGPR
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// vexCountGPR is the three-operand count form over general-purpose
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// registers (SHLX, SHRX, SARX, BEXTR, BZHI): the first operand rides
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// VEX.vvvv and the second is r/m, the opposite pairing of the ANDN
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// family, with reg = dst (op2), L = 0.
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vexCountGPR
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// vexExtractGPR is the lane-extract-to-GPR form `OP $imm, xsrc, GPR/mem
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// dst`: ModRM.reg = xsrc (op1), ModRM.rm = destination (op2), imm8 =
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// op0, the VPEXTRB/W/D/Q layout. EVEX only; the destination never
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// carries a vector length, so the register the L'L field follows is the
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// XMM source.
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vexExtractGPR
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)
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// vexSpec describes one VEX instruction's encoding parameters.
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@@ -230,8 +245,34 @@ var vexTable = map[string]vexSpec{
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"ANDNQ": {2, 0xF2, 1, 0, -1, vexNDS3GPR},
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"MULXL": {2, 0xF6, 0, 3, -1, vexNDS3GPR},
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"MULXQ": {2, 0xF6, 1, 3, -1, vexNDS3GPR},
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"RORXL": {3, 0xF0, 0, 3, -1, vexImmRMGPR},
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"RORXQ": {3, 0xF0, 1, 3, -1, vexImmRMGPR},
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// VEX.NDS.LZ.0F38, the BMI2 three-operand bit ops: BEXTR and BZHI
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// share the F7/F5 opcodes across W, the variable shifts carry their
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// direction in the prefix (SHLX 66, SHRX F2, SARX F3) and PDEP/PEXT
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// in F2/F3.
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"BEXTRL": {2, 0xF7, 0, 0, -1, vexCountGPR},
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"BEXTRQ": {2, 0xF7, 1, 0, -1, vexCountGPR},
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"BZHIL": {2, 0xF5, 0, 0, -1, vexCountGPR},
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"BZHIQ": {2, 0xF5, 1, 0, -1, vexCountGPR},
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"SARXL": {2, 0xF7, 0, 2, -1, vexCountGPR},
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"SARXQ": {2, 0xF7, 1, 2, -1, vexCountGPR},
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"SHLXL": {2, 0xF7, 0, 1, -1, vexCountGPR},
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"SHLXQ": {2, 0xF7, 1, 1, -1, vexCountGPR},
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"SHRXL": {2, 0xF7, 0, 3, -1, vexCountGPR},
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"SHRXQ": {2, 0xF7, 1, 3, -1, vexCountGPR},
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"PDEPL": {2, 0xF5, 0, 3, -1, vexNDS3GPR},
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"PDEPQ": {2, 0xF5, 1, 3, -1, vexNDS3GPR},
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"PEXTL": {2, 0xF5, 0, 2, -1, vexNDS3GPR},
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"PEXTQ": {2, 0xF5, 1, 2, -1, vexNDS3GPR},
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// VEX.LZ.0F38.W, the BMI1 unary bit ops (src, dst: ModRM.reg = /digit,
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// rm = src, vvvv = dst).
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"BLSIL": {2, 0xF3, 0, 0, 3, vexRMOpGPR},
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"BLSIQ": {2, 0xF3, 1, 0, 3, vexRMOpGPR},
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"BLSMSKL": {2, 0xF3, 0, 0, 2, vexRMOpGPR},
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"BLSMSKQ": {2, 0xF3, 1, 0, 2, vexRMOpGPR},
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"BLSRL": {2, 0xF3, 0, 0, 1, vexRMOpGPR},
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"BLSRQ": {2, 0xF3, 1, 0, 1, vexRMOpGPR},
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"RORXL": {3, 0xF0, 0, 3, -1, vexImmRMGPR},
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"RORXQ": {3, 0xF0, 1, 3, -1, vexImmRMGPR},
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// VEX.128.0F.W0, mask-register test (KTESTW k1, k2: reg = dst, rm = src).
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"KTESTW": {1, 0x99, 0, 0, -1, vexRM},
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@@ -290,6 +331,128 @@ var vexTable = map[string]vexSpec{
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"VCVTPD2DQY": {1, 0xE6, 0, 3, -1, vexRMSrcLen},
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"VCVTTPD2DQX": {1, 0xE6, 0, 1, -1, vexRMSrcLen},
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"VCVTTPD2DQY": {1, 0xE6, 0, 1, -1, vexRMSrcLen},
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// --- the VEX forms the avx512enc corpus exercises alongside the EVEX
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// spellings, read off the toolchain opcode tables ---
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"VAESDEC": {2, 0xDE, 0, 1, -1, vexNDS3},
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"VAESDECLAST": {2, 0xDF, 0, 1, -1, vexNDS3},
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"VAESENC": {2, 0xDC, 0, 1, -1, vexNDS3},
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"VAESENCLAST": {2, 0xDD, 0, 1, -1, vexNDS3},
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"VANDNPD": {1, 0x55, 0, 1, -1, vexNDS3},
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"VANDPD": {1, 0x54, 0, 1, -1, vexNDS3},
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"VCOMISD": {1, 0x2F, 0, 1, -1, vexRM},
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"VCVTSD2SS": {1, 0x5A, 0, 3, -1, vexNDS3},
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"VCVTSS2SD": {1, 0x5A, 0, 2, -1, vexNDS3},
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"VFMADD132PD": {2, 0x98, 1, 1, -1, vexNDS3},
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"VFMADD132PS": {2, 0x98, 0, 1, -1, vexNDS3},
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"VFMADD132SD": {2, 0x99, 1, 1, -1, vexNDS3},
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"VFMADD132SS": {2, 0x99, 0, 1, -1, vexNDS3},
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"VFMADD213PD": {2, 0xA8, 1, 1, -1, vexNDS3},
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"VFMADD213PS": {2, 0xA8, 0, 1, -1, vexNDS3},
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"VFMADD213SS": {2, 0xA9, 0, 1, -1, vexNDS3},
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"VFMADD231PS": {2, 0xB8, 0, 1, -1, vexNDS3},
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"VFMADD231SD": {2, 0xB9, 1, 1, -1, vexNDS3},
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"VFMADD231SS": {2, 0xB9, 0, 1, -1, vexNDS3},
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"VFMADDSUB132PD": {2, 0x96, 1, 1, -1, vexNDS3},
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"VFMADDSUB132PS": {2, 0x96, 0, 1, -1, vexNDS3},
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"VFMADDSUB213PD": {2, 0xA6, 1, 1, -1, vexNDS3},
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"VFMADDSUB213PS": {2, 0xA6, 0, 1, -1, vexNDS3},
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"VFMADDSUB231PD": {2, 0xB6, 1, 1, -1, vexNDS3},
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"VFMADDSUB231PS": {2, 0xB6, 0, 1, -1, vexNDS3},
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"VFMSUB132PD": {2, 0x9A, 1, 1, -1, vexNDS3},
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"VFMSUB132PS": {2, 0x9A, 0, 1, -1, vexNDS3},
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"VFMSUB132SD": {2, 0x9B, 1, 1, -1, vexNDS3},
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"VFMSUB132SS": {2, 0x9B, 0, 1, -1, vexNDS3},
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"VFMSUB213PD": {2, 0xAA, 1, 1, -1, vexNDS3},
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"VFMSUB213PS": {2, 0xAA, 0, 1, -1, vexNDS3},
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"VFMSUB213SD": {2, 0xAB, 1, 1, -1, vexNDS3},
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"VFMSUB213SS": {2, 0xAB, 0, 1, -1, vexNDS3},
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"VFMSUB231PD": {2, 0xBA, 1, 1, -1, vexNDS3},
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"VFMSUB231PS": {2, 0xBA, 0, 1, -1, vexNDS3},
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"VFMSUB231SD": {2, 0xBB, 1, 1, -1, vexNDS3},
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"VFMSUB231SS": {2, 0xBB, 0, 1, -1, vexNDS3},
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"VFMSUBADD132PD": {2, 0x97, 1, 1, -1, vexNDS3},
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"VFMSUBADD132PS": {2, 0x97, 0, 1, -1, vexNDS3},
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"VFMSUBADD213PD": {2, 0xA7, 1, 1, -1, vexNDS3},
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"VFMSUBADD213PS": {2, 0xA7, 0, 1, -1, vexNDS3},
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"VFMSUBADD231PD": {2, 0xB7, 1, 1, -1, vexNDS3},
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"VFMSUBADD231PS": {2, 0xB7, 0, 1, -1, vexNDS3},
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"VFNMADD132PD": {2, 0x9C, 1, 1, -1, vexNDS3},
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"VFNMADD132PS": {2, 0x9C, 0, 1, -1, vexNDS3},
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"VFNMADD132SD": {2, 0x9D, 1, 1, -1, vexNDS3},
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"VFNMADD132SS": {2, 0x9D, 0, 1, -1, vexNDS3},
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"VFNMADD213PD": {2, 0xAC, 1, 1, -1, vexNDS3},
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"VFNMADD213PS": {2, 0xAC, 0, 1, -1, vexNDS3},
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"VFNMADD213SD": {2, 0xAD, 1, 1, -1, vexNDS3},
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"VFNMADD213SS": {2, 0xAD, 0, 1, -1, vexNDS3},
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"VFNMADD231PD": {2, 0xBC, 1, 1, -1, vexNDS3},
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"VFNMADD231PS": {2, 0xBC, 0, 1, -1, vexNDS3},
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"VFNMADD231SS": {2, 0xBD, 0, 1, -1, vexNDS3},
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"VFNMSUB132PD": {2, 0x9E, 1, 1, -1, vexNDS3},
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"VFNMSUB132PS": {2, 0x9E, 0, 1, -1, vexNDS3},
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"VFNMSUB132SD": {2, 0x9F, 1, 1, -1, vexNDS3},
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"VFNMSUB132SS": {2, 0x9F, 0, 1, -1, vexNDS3},
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"VFNMSUB213PD": {2, 0xAE, 1, 1, -1, vexNDS3},
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"VFNMSUB213PS": {2, 0xAE, 0, 1, -1, vexNDS3},
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"VFNMSUB213SD": {2, 0xAF, 1, 1, -1, vexNDS3},
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"VFNMSUB213SS": {2, 0xAF, 0, 1, -1, vexNDS3},
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"VFNMSUB231PD": {2, 0xBE, 1, 1, -1, vexNDS3},
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"VFNMSUB231PS": {2, 0xBE, 0, 1, -1, vexNDS3},
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"VFNMSUB231SD": {2, 0xBF, 1, 1, -1, vexNDS3},
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"VFNMSUB231SS": {2, 0xBF, 0, 1, -1, vexNDS3},
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"VGF2P8AFFINEINVQB": {3, 0xCF, 1, 1, -1, vexNDS3Imm},
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"VGF2P8MULB": {2, 0xCF, 0, 1, -1, vexNDS3},
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"VMOVNTDQA": {2, 0x2A, 0, 1, -1, vexRM},
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"VMOVNTPD": {1, 0x2B, 0, 1, -1, vexRMRev},
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"VORPD": {1, 0x56, 0, 1, -1, vexNDS3},
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"VPADDSB": {1, 0xEC, 0, 1, -1, vexNDS3},
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"VPADDSW": {1, 0xED, 0, 1, -1, vexNDS3},
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"VPADDUSB": {1, 0xDC, 0, 1, -1, vexNDS3},
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"VPADDUSW": {1, 0xDD, 0, 1, -1, vexNDS3},
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"VPCMPEQQ": {2, 0x29, 0, 1, -1, vexNDS3},
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"VPCMPEQW": {1, 0x75, 0, 1, -1, vexNDS3},
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"VPCMPGTB": {1, 0x64, 0, 1, -1, vexNDS3},
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"VPCMPGTD": {1, 0x66, 0, 1, -1, vexNDS3},
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"VPCMPGTW": {1, 0x65, 0, 1, -1, vexNDS3},
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"VPERMPS": {2, 0x16, 0, 1, -1, vexNDS3},
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"VPEXTRB": {3, 0x14, 0, 1, -1, vexExtract},
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"VPEXTRD": {3, 0x16, 0, 1, -1, vexExtract},
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"VPEXTRQ": {3, 0x16, 1, 1, -1, vexExtract},
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"VPINSRD": {3, 0x22, 0, 1, -1, vexNDS3Imm},
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"VPINSRQ": {3, 0x22, 1, 1, -1, vexNDS3Imm},
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"VPMULHRSW": {2, 0x0B, 0, 1, -1, vexNDS3},
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"VPMULHW": {1, 0xE5, 0, 1, -1, vexNDS3},
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"VPMULUDQ": {1, 0xF4, 0, 1, -1, vexNDS3},
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"VPSADBW": {1, 0xF6, 0, 1, -1, vexNDS3},
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"VPSUBSB": {1, 0xE8, 0, 1, -1, vexNDS3},
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"VPSUBSW": {1, 0xE9, 0, 1, -1, vexNDS3},
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"VPSUBUSB": {1, 0xD8, 0, 1, -1, vexNDS3},
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"VPSUBUSW": {1, 0xD9, 0, 1, -1, vexNDS3},
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"VPUNPCKHBW": {1, 0x68, 0, 1, -1, vexNDS3},
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"VPUNPCKHQDQ": {1, 0x6D, 0, 1, -1, vexNDS3},
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"VPUNPCKHWD": {1, 0x69, 0, 1, -1, vexNDS3},
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"VPUNPCKLBW": {1, 0x60, 0, 1, -1, vexNDS3},
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"VPUNPCKLWD": {1, 0x61, 0, 1, -1, vexNDS3},
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"VSQRTPD": {1, 0x51, 0, 1, -1, vexRM},
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"VSQRTSD": {1, 0x51, 0, 3, -1, vexNDS3},
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"VSQRTSS": {1, 0x51, 0, 2, -1, vexNDS3},
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"VUCOMISD": {1, 0x2E, 0, 1, -1, vexRM},
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// VEX.0F.WIG, the plain-prefix single/double arithmetic and unpack
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// spellings (no 66 prefix; WIG, so W = 0).
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"VANDNPS": {1, 0x55, 0, 0, -1, vexNDS3},
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"VANDPS": {1, 0x54, 0, 0, -1, vexNDS3},
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"VORPS": {1, 0x56, 0, 0, -1, vexNDS3},
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"VUNPCKLPS": {1, 0x14, 0, 0, -1, vexNDS3},
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"VUNPCKHPS": {1, 0x15, 0, 0, -1, vexNDS3},
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"VSQRTPS": {1, 0x51, 0, 0, -1, vexRM},
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"VMOVNTPS": {1, 0x2B, 0, 0, -1, vexRMRev},
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// VEX.128.66.0F, the scalar and packed compare forms.
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"VCOMISS": {1, 0x2F, 0, 1, -1, vexRM},
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"VUCOMISS": {1, 0x2E, 0, 0, -1, vexRM},
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// VEX.128.0F.F3/F2.W0, the high/low word shuffles ($imm, src, dst).
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"VPSHUFHW": {1, 0x70, 0, 2, -1, vexImmRM},
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"VPSHUFLW": {1, 0x70, 0, 3, -1, vexImmRM},
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}
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// vexSrcLen maps a source-length conversion mnemonic (the X/Y spellings of
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@@ -420,6 +583,10 @@ func (e *enc) encodeVex(mnemUpper string, ops []Operand) error {
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return e.encodeVexNDS3GPR(spec, ops)
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case vexImmRMGPR:
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return e.encodeVexImmRMGPR(spec, ops)
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case vexRMOpGPR:
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return e.encodeVexRMOpGPR(spec, ops)
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case vexCountGPR:
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return e.encodeVexCountGPR(spec, ops)
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case vexRMRev:
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return e.encodeVexRMRev(spec, ops)
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}
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@@ -523,9 +690,10 @@ func (e *enc) encodeVexShiftImm(spec vexSpec, ops []Operand) error {
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if !ok {
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return fmt.Errorf("shift count must be an immediate")
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}
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srcReg, ok := src.(Reg)
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if !ok || !srcReg.isVec() {
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return fmt.Errorf("shift source must be a vector register")
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// The count source is a vector register or memory; the VEX length
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// follows the destination register either way.
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if !vecOrMem(src) {
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return fmt.Errorf("shift source must be a vector register or memory")
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}
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dstReg, ok := dst.(Reg)
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if !ok || !dstReg.isVec() {
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@@ -533,7 +701,7 @@ func (e *enc) encodeVexShiftImm(spec vexSpec, ops []Operand) error {
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}
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vvvvBar := 15 - (dstReg.idx & 15)
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if err := e.emitVexFields(spec, dstReg.vecLenBit(), spec.opdigit, 0, vvvvBar, srcReg); err != nil {
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if err := e.emitVexFields(spec, dstReg.vecLenBit(), spec.opdigit, 0, vvvvBar, src); err != nil {
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return err
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}
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immByte, err := imm8(int64(immVal))
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@@ -700,7 +868,11 @@ func (e *enc) encodeVexNDS3GPR(spec vexSpec, ops []Operand) error {
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if !ok || vvvvReg.isVec() {
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return fmt.Errorf("VEX vvvv operand must be a general-purpose register")
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}
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return e.emitVexFields(spec, 0, dstReg.idx&7, 0, 15-(vvvvReg.idx&15), src2)
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rBit := 0
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if dstReg.idx >= 8 {
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rBit = 1
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}
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return e.emitVexFields(spec, 0, dstReg.idx&7, rBit, 15-(vvvvReg.idx&15), src2)
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}
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// encodeVexImmRMGPR encodes the immediate form over general-purpose
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@@ -729,6 +901,48 @@ func (e *enc) encodeVexImmRMGPR(spec vexSpec, ops []Operand) error {
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return nil
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}
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// encodeVexRMOpGPR encodes the two-operand /digit form over general-purpose
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// registers (BLSI, BLSMSK, BLSR): OP src, dst with ModRM.reg = /digit,
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// ModRM.rm = src and VEX.vvvv = dst.
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func (e *enc) encodeVexRMOpGPR(spec vexSpec, ops []Operand) error {
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if len(ops) != 2 {
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return fmt.Errorf("instruction expects 2 operands (src, dst), got %d", len(ops))
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}
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src, dst := ops[0], ops[1]
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dstReg, ok := dst.(Reg)
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if !ok || dstReg.isVec() {
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return fmt.Errorf("VEX destination must be a general-purpose register")
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}
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return e.emitVexFields(spec, 0, spec.opdigit, 0, 15-(dstReg.idx&15), src)
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}
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// encodeVexCountGPR encodes the three-operand count form over general-purpose
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// registers (SHLX, SHRX, SARX, BEXTR, BZHI): OP src, count, dst with
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// VEX.vvvv = src (op0), ModRM.rm = count (op1), ModRM.reg = dst (op2).
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func (e *enc) encodeVexCountGPR(spec vexSpec, ops []Operand) error {
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if len(ops) != 3 {
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return fmt.Errorf("VEX count instruction expects 3 operands, got %d", len(ops))
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}
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src, count, dst := ops[0], ops[1], ops[2]
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dstReg, ok := dst.(Reg)
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if !ok || dstReg.isVec() {
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return fmt.Errorf("VEX destination must be a general-purpose register")
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}
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countReg, ok := count.(Reg)
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if !ok || countReg.isVec() {
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return fmt.Errorf("VEX count operand must be a general-purpose register")
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}
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srcReg, ok := src.(Reg)
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if !ok || srcReg.isVec() {
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return fmt.Errorf("VEX count source must be a general-purpose register")
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}
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rBit := 0
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if dstReg.idx >= 8 {
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rBit = 1
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}
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return e.emitVexFields(spec, 0, dstReg.idx&7, rBit, 15-(srcReg.idx&15), count)
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}
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// encodeVexRMRev encodes the reversed two-operand form: OP src, dst with the
|
||||
// vector source in ModRM.reg and the memory destination in r/m (VMOVNTDQ,
|
||||
// a store with no register-destination form).
|
||||
|
||||
@@ -31,6 +31,51 @@ var x86asmUnrecognised = map[string]bool{
|
||||
"RORXQ": true,
|
||||
"VFMADD213SD": true,
|
||||
"VFNMADD231SD": true,
|
||||
// The scalar FMA spellings the decoder's tables lack entirely.
|
||||
"VFMADD132SD": true,
|
||||
"VFMADD132SS": true,
|
||||
"VFMADD213SS": true,
|
||||
"VFMADD231SD": true,
|
||||
"VFMADD231SS": true,
|
||||
"VFMSUB132SD": true,
|
||||
"VFMSUB132SS": true,
|
||||
"VFMSUB213SD": true,
|
||||
"VFMSUB213SS": true,
|
||||
"VFMSUB231SD": true,
|
||||
"VFMSUB231SS": true,
|
||||
"VFNMADD132SD": true,
|
||||
"VFNMADD132SS": true,
|
||||
"VFNMADD213SD": true,
|
||||
"VFNMADD213SS": true,
|
||||
"VFNMADD231SS": true,
|
||||
"VFNMSUB132SD": true,
|
||||
"VFNMSUB132SS": true,
|
||||
"VFNMSUB213SD": true,
|
||||
"VFNMSUB213SS": true,
|
||||
"VFNMSUB231SD": true,
|
||||
"VFNMSUB231SS": true,
|
||||
// The BMI1 unary bit ops the decoder's AVX tables lack.
|
||||
"BLSIL": true,
|
||||
"BLSIQ": true,
|
||||
"BLSMSKL": true,
|
||||
"BLSMSKQ": true,
|
||||
"BLSRL": true,
|
||||
"BLSRQ": true,
|
||||
// The BMI2 bit ops whose W1/LZ rows the decoder misses.
|
||||
"BEXTRL": true,
|
||||
"BEXTRQ": true,
|
||||
"BZHIL": true,
|
||||
"BZHIQ": true,
|
||||
"PDEPL": true,
|
||||
"PDEPQ": true,
|
||||
"PEXTL": true,
|
||||
"PEXTQ": true,
|
||||
"SARXL": true,
|
||||
"SARXQ": true,
|
||||
"SHLXL": true,
|
||||
"SHLXQ": true,
|
||||
"SHRXL": true,
|
||||
"SHRXQ": true,
|
||||
}
|
||||
|
||||
// TestVexNDS3 encodes `mnem Y0, Y1, Y2` for every three-operand NDS
|
||||
@@ -237,6 +282,18 @@ func TestVexGroundTruth(t *testing.T) {
|
||||
{"MULXQ AX,BX,CX", "MULXQ", []Operand{AX, BX, CX}, "c4e2e3f6c8", ""},
|
||||
{"RORXL $3,AX,CX", "RORXL", []Operand{Imm(3), AX, CX}, "c4e37bf0c803", ""},
|
||||
{"RORXQ $3,AX,CX", "RORXQ", []Operand{Imm(3), AX, CX}, "c4e3fbf0c803", ""},
|
||||
// BMI2 variable shifts and bit ops (three general registers).
|
||||
{"SHLXL AX,CX,R15", "SHLXL", []Operand{AX, CX, vreg(t, "R15")}, "c46279f7f9", ""},
|
||||
{"SHRXQ R8,DX,AX", "SHRXQ", []Operand{vreg(t, "R8"), DX, AX}, "c4e2bbf7c2", ""},
|
||||
{"SARXQ AX,DX,R9", "SARXQ", []Operand{AX, DX, vreg(t, "R9")}, "c462faf7ca", ""},
|
||||
{"BEXTRL AX,CX,R15", "BEXTRL", []Operand{AX, CX, vreg(t, "R15")}, "c46278f7f9", ""},
|
||||
{"BZHIQ AX,CX,R15", "BZHIQ", []Operand{AX, CX, vreg(t, "R15")}, "c462f8f5f9", ""},
|
||||
{"PDEPQ AX,CX,R15", "PDEPQ", []Operand{AX, CX, vreg(t, "R15")}, "c462f3f5f8", ""},
|
||||
{"PEXTQ AX,CX,R15", "PEXTQ", []Operand{AX, CX, vreg(t, "R15")}, "c462f2f5f8", ""},
|
||||
// BMI1 unary bit ops (src, dst: /digit in ModRM.reg, dst in vvvv).
|
||||
{"BLSIL AX,CX", "BLSIL", []Operand{AX, CX}, "c4e270f3d8", ""},
|
||||
{"BLSRQ AX,CX", "BLSRQ", []Operand{AX, CX}, "c4e2f0f3c8", ""},
|
||||
{"BLSMSKQ AX,CX", "BLSMSKQ", []Operand{AX, CX}, "c4e2f0f3d0", ""},
|
||||
// Two-operand reg/rm form (v̄vvv must be 1111).
|
||||
{"VPMOVSXDQ X0,Y4", "VPMOVSXDQ", []Operand{vreg(t, "X0"), vreg(t, "Y4")}, "c4e27d25e0", ""},
|
||||
{"VPMOVSXWD (SI),Y0", "VPMOVSXWD", []Operand{Ptr(SI, 0, 8), vreg(t, "Y0")}, "c4e27d2306", ""},
|
||||
|
||||
@@ -34,6 +34,8 @@ func TestGroundTruthARM64(t *testing.T) {
|
||||
"../testdata/verify/simd_arm64.s",
|
||||
"../testdata/verify/widenimm_arm64.s",
|
||||
"../testdata/verify/carryshift_arm64.s",
|
||||
"../testdata/verify/simdmove_arm64.s",
|
||||
"../testdata/verify/bookkeep_arm64.s",
|
||||
"../testdata/verify/system_arm64.s",
|
||||
} {
|
||||
t.Run(path, func(t *testing.T) {
|
||||
|
||||
@@ -124,8 +124,10 @@ func TestGroundTruthAMD64(t *testing.T) {
|
||||
"../testdata/verify/avx_amd64.s",
|
||||
"../testdata/verify/pfx_amd64.s",
|
||||
"../testdata/verify/rawdata_amd64.s",
|
||||
"../testdata/verify/avx512_amd64.s",
|
||||
"../testdata/verify/pfx_amd64.s",
|
||||
"../testdata/verify/rawdata_amd64.s",
|
||||
"../testdata/verify/avx512_amd64.s",
|
||||
"../testdata/verify/doubleshift_amd64.s",
|
||||
"../testdata/verify/ssestatic_amd64.s",
|
||||
} {
|
||||
|
||||
Reference in New Issue
Block a user