fix(asm): key the arm64 immediate class order on the ZR spelling

Assisted-by: GLM 5.3 Flash

asm/arm64_encode_test.go

@@ -2157,3 +2157,31 @@ func TestArm64LogicalImmZR(t *testing.T) {
 		}
 	}
 }
+
+// TestArm64ZRNameNotNumber pins the spellings where ZR and RSP share the
+// register number but not the class: the toolchain's omovconst guards the
+// bitmask path with rt != REGZERO, so RSP keeps the fast logical and ORR
+// forms while ZR materialises or rides MOVZ.
+func TestArm64ZRNameNotNumber(t *testing.T) {
+	got := arm64Words(t,
+		"\tAND $8, R0, RSP\n"+
+			"\tORR $8, R0, RSP\n"+
+			"\tMOVW $0x10001000, RSP\n"+
+			"\tADDW $0x10001000, R1\n")
+	want := []uint32{
+		0x927d001f, // AND X31(SP), X0, #bitmask: the fast path for RSP
+		0xb27d001f, // ORR X31(SP), X0, #bitmask
+		0x320483ff, // ORR W31(SP), WZR, #0x10001000 (the MOVW bitmask)
+		0x320483fb, // ORR W27, WZR, #0x10001000
+		0x0b1b0021, // ADDW W1, W1, W27
+		0xd65f03c0, // RET
+	}
+	if len(got) != len(want) {
+		t.Fatalf("word count = %d, want %d", len(got), len(want))
+	}
+	for i := range want {
+		if got[i] != want[i] {
+			t.Errorf("word %d = %08x, want %08x", i, got[i], want[i])
+		}
+	}
+}