feat(arch): the SVE2 BFloat16 arithmetic core
Assisted-by: GLM 5.3 Flash
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@@ -2036,8 +2036,12 @@ func (in ExtInstr) encodeVectorsZm(ops []ExtOperand) ([]byte, error) {
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// riding the destination's arrangement.
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func (in ExtInstr) encodeZUnpack(ops []ExtOperand) ([]byte, error) {
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pn, zd := ops[0], ops[1]
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if err := in.zVector(pn, 1); err != nil {
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return nil, err
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if pn.Kind != ExtZReg {
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return nil, fmt.Errorf("%s: operand 1 wants a scalable vector register, got %s",
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in.Name, pn.Kind)
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}
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if pn.Reg < 0 || pn.Reg > 31 {
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return nil, fmt.Errorf("%s: operand 1 is Z%d, outside Z0-Z31", in.Name, pn.Reg)
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}
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if pn.Arr != ExtArrB {
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return nil, fmt.Errorf("%s: operand 1 carries arrangement %s, want .B", in.Name, pn.Arr)
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@@ -3426,6 +3430,63 @@ var arm64Extensions = []ExtInstr{
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Word: 0x04e03c00, Form: ExtFormThreeSource, Arr: ExtArrD, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZNBSL; inst_gen.go + arm64sveenc.s"},
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// --- the SVE2 BFloat16 arithmetic core ------------------------------------
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//
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// The two-shape arithmetic (ADD, MAX, MAXNM, MIN, MINNM, MUL, SUB)
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// over halfwords only: the predicated-source and unpredicated
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// three-vector spellings, the clamp over the unpredicated shape, and
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// the B-to-H conversions of the F1CVT and F2CVT pairs. The remaining
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// BFloat16 shapes (dot products, lengthened multiplies, converts with
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// a governing predicate) stay unwired. Provenance as above: the
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// toolchain encoding table and its generated corpus, both produced
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// from Arm's official ISA description, and the golden test pins every
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// corpus line of the covered classes.
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{Name: "ZBF1CVT", Summary: "Convert BFloat16 pairs from bytes to halfwords, bottom",
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Word: 0x65083800, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBF1CVT; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBF1CVTLT", Summary: "Convert BFloat16 pairs from bytes to halfwords, bottom, no rounding",
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Word: 0x65093800, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBF1CVTLT; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBF2CVT", Summary: "Convert BFloat16 pairs from bytes to halfwords, top",
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Word: 0x65083c00, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBF2CVT; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBF2CVTLT", Summary: "Convert BFloat16 pairs from bytes to halfwords, top, no rounding",
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Word: 0x65093c00, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBF2CVTLT; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBFADD", Summary: "Add BFloat16 halfwords, merging",
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Word: 0x65008000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBFADD; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBFADD", Summary: "Add BFloat16 halfwords, unpredicated",
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Word: 0x65000000, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBFADD; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBFCLAMP", Summary: "Clamp BFloat16 halfwords between bounds, unpredicated",
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Word: 0x64202400, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBFCLAMP; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBFMAX", Summary: "Maximum of BFloat16 halfwords, merging",
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Word: 0x65068000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBFMAX; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBFMAXNM", Summary: "Maximum number of BFloat16 halfwords, merging",
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Word: 0x65048000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBFMAXNM; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBFMIN", Summary: "Minimum of BFloat16 halfwords, merging",
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Word: 0x65078000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBFMIN; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBFMINNM", Summary: "Minimum number of BFloat16 halfwords, merging",
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Word: 0x65058000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBFMINNM; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBFMUL", Summary: "Multiply BFloat16 halfwords, merging",
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Word: 0x65028000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBFMUL; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBFMUL", Summary: "Multiply BFloat16 halfwords, unpredicated",
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Word: 0x65000800, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBFMUL; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBFSUB", Summary: "Subtract BFloat16 halfwords, merging",
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Word: 0x65018000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBFSUB; inst_gen.go + arm64sveenc.s"},
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{Name: "ZBFSUB", Summary: "Subtract BFloat16 halfwords, unpredicated",
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Word: 0x65000400, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
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Ref: "ARM DDI 0487J SVE2: ZBFSUB; inst_gen.go + arm64sveenc.s"},
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// --- the SVE2 crypto family ----------------------------------------------
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//
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// The multi-precision carry steps (ADCLB, ADCLT, SBCLB, SBCLT), the SHA3
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@@ -1505,6 +1505,52 @@ func TestArm64ExtStage4Golden(t *testing.T) {
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{"ZEORTB Z7.D, Z23.D, Z13.D", "ZEORTB", ExtFormVectorsZm, ExtQualNone, ExtArrNone,
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[]ExtOperand{ExtVector(7, ExtArrD), ExtVector(23, ExtArrD), ExtVector(13, ExtArrD)},
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0x45c796ed},
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// The BFloat16 arithmetic core, halfwords throughout.
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{"ZBF1CVT Z11.B, Z6.H", "ZBF1CVT", ExtFormZUnpack, ExtQualNone, ExtArrH,
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[]ExtOperand{ExtVector(11, ExtArrB), ExtVector(6, ExtArrH)},
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0x65083966},
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{"ZBF1CVTLT Z11.B, Z6.H", "ZBF1CVTLT", ExtFormZUnpack, ExtQualNone, ExtArrH,
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[]ExtOperand{ExtVector(11, ExtArrB), ExtVector(6, ExtArrH)},
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0x65093966},
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{"ZBF2CVT Z11.B, Z6.H", "ZBF2CVT", ExtFormZUnpack, ExtQualNone, ExtArrH,
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[]ExtOperand{ExtVector(11, ExtArrB), ExtVector(6, ExtArrH)},
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0x65083d66},
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{"ZBF2CVTLT Z11.B, Z6.H", "ZBF2CVTLT", ExtFormZUnpack, ExtQualNone, ExtArrH,
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[]ExtOperand{ExtVector(11, ExtArrB), ExtVector(6, ExtArrH)},
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0x65093d66},
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{"ZBFADD Z23.H, Z13.H, P1.M, Z13.H", "ZBFADD", ExtFormZPredicatedSource, ExtQualMerging, ExtArrH,
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[]ExtOperand{ExtVector(23, ExtArrH), ExtVector(13, ExtArrH), ExtPredicate(1, ExtQualMerging), ExtVector(13, ExtArrH)},
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0x650086ed},
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{"ZBFADD Z7.H, Z6.H, Z23.H", "ZBFADD", ExtFormVectorsZm, ExtQualNone, ExtArrH,
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[]ExtOperand{ExtVector(7, ExtArrH), ExtVector(6, ExtArrH), ExtVector(23, ExtArrH)},
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0x650700d7},
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{"ZBFCLAMP Z7.H, Z6.H, Z23.H", "ZBFCLAMP", ExtFormVectorsZm, ExtQualNone, ExtArrH,
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[]ExtOperand{ExtVector(7, ExtArrH), ExtVector(6, ExtArrH), ExtVector(23, ExtArrH)},
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0x642724d7},
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{"ZBFMAX Z23.H, Z13.H, P1.M, Z13.H", "ZBFMAX", ExtFormZPredicatedSource, ExtQualMerging, ExtArrH,
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[]ExtOperand{ExtVector(23, ExtArrH), ExtVector(13, ExtArrH), ExtPredicate(1, ExtQualMerging), ExtVector(13, ExtArrH)},
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0x650686ed},
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{"ZBFMAXNM Z23.H, Z13.H, P1.M, Z13.H", "ZBFMAXNM", ExtFormZPredicatedSource, ExtQualMerging, ExtArrH,
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[]ExtOperand{ExtVector(23, ExtArrH), ExtVector(13, ExtArrH), ExtPredicate(1, ExtQualMerging), ExtVector(13, ExtArrH)},
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0x650486ed},
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{"ZBFMIN Z23.H, Z13.H, P1.M, Z13.H", "ZBFMIN", ExtFormZPredicatedSource, ExtQualMerging, ExtArrH,
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[]ExtOperand{ExtVector(23, ExtArrH), ExtVector(13, ExtArrH), ExtPredicate(1, ExtQualMerging), ExtVector(13, ExtArrH)},
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0x650786ed},
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{"ZBFMINNM Z23.H, Z13.H, P1.M, Z13.H", "ZBFMINNM", ExtFormZPredicatedSource, ExtQualMerging, ExtArrH,
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[]ExtOperand{ExtVector(23, ExtArrH), ExtVector(13, ExtArrH), ExtPredicate(1, ExtQualMerging), ExtVector(13, ExtArrH)},
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0x650586ed},
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{"ZBFMUL Z23.H, Z13.H, P1.M, Z13.H", "ZBFMUL", ExtFormZPredicatedSource, ExtQualMerging, ExtArrH,
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[]ExtOperand{ExtVector(23, ExtArrH), ExtVector(13, ExtArrH), ExtPredicate(1, ExtQualMerging), ExtVector(13, ExtArrH)},
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0x650286ed},
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{"ZBFMUL Z7.H, Z6.H, Z23.H", "ZBFMUL", ExtFormVectorsZm, ExtQualNone, ExtArrH,
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[]ExtOperand{ExtVector(7, ExtArrH), ExtVector(6, ExtArrH), ExtVector(23, ExtArrH)},
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0x650708d7},
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{"ZBFSUB Z23.H, Z13.H, P1.M, Z13.H", "ZBFSUB", ExtFormZPredicatedSource, ExtQualMerging, ExtArrH,
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[]ExtOperand{ExtVector(23, ExtArrH), ExtVector(13, ExtArrH), ExtPredicate(1, ExtQualMerging), ExtVector(13, ExtArrH)},
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0x650186ed},
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{"ZBFSUB Z7.H, Z6.H, Z23.H", "ZBFSUB", ExtFormVectorsZm, ExtQualNone, ExtArrH,
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[]ExtOperand{ExtVector(7, ExtArrH), ExtVector(6, ExtArrH), ExtVector(23, ExtArrH)},
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0x650704d7},
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} {
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in := extInstructionMeta(t, tt.mnem, tt.form, tt.qual, tt.arr)
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got, err := in.Encode(tt.ops)
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