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feat(arch): the SVE2 BFloat16 arithmetic core

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Assisted-by: GLM 5.3 Flash
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petrbalvin committed 2026-10-07 20:35:41 +02:00
1 parent 0760cc91af
commit 82dbf087a8
4 files changed
+139 -4
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arch/arm64_ext.go
+63 -2
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@@ -2036,8 +2036,12 @@ func (in ExtInstr) encodeVectorsZm(ops []ExtOperand) ([]byte, error) {
// riding the destination's arrangement.
func (in ExtInstr) encodeZUnpack(ops []ExtOperand) ([]byte, error) {
pn, zd := ops[0], ops[1]
if err := in.zVector(pn, 1); err != nil {
return nil, err
if pn.Kind != ExtZReg {
return nil, fmt.Errorf("%s: operand 1 wants a scalable vector register, got %s",
in.Name, pn.Kind)
}
if pn.Reg < 0 || pn.Reg > 31 {
return nil, fmt.Errorf("%s: operand 1 is Z%d, outside Z0-Z31", in.Name, pn.Reg)
}
if pn.Arr != ExtArrB {
return nil, fmt.Errorf("%s: operand 1 carries arrangement %s, want .B", in.Name, pn.Arr)
@@ -3426,6 +3430,63 @@ var arm64Extensions = []ExtInstr{
Word: 0x04e03c00, Form: ExtFormThreeSource, Arr: ExtArrD, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZNBSL; inst_gen.go + arm64sveenc.s"},
// --- the SVE2 BFloat16 arithmetic core ------------------------------------
//
// The two-shape arithmetic (ADD, MAX, MAXNM, MIN, MINNM, MUL, SUB)
// over halfwords only: the predicated-source and unpredicated
// three-vector spellings, the clamp over the unpredicated shape, and
// the B-to-H conversions of the F1CVT and F2CVT pairs. The remaining
// BFloat16 shapes (dot products, lengthened multiplies, converts with
// a governing predicate) stay unwired. Provenance as above: the
// toolchain encoding table and its generated corpus, both produced
// from Arm's official ISA description, and the golden test pins every
// corpus line of the covered classes.
{Name: "ZBF1CVT", Summary: "Convert BFloat16 pairs from bytes to halfwords, bottom",
Word: 0x65083800, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBF1CVT; inst_gen.go + arm64sveenc.s"},
{Name: "ZBF1CVTLT", Summary: "Convert BFloat16 pairs from bytes to halfwords, bottom, no rounding",
Word: 0x65093800, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBF1CVTLT; inst_gen.go + arm64sveenc.s"},
{Name: "ZBF2CVT", Summary: "Convert BFloat16 pairs from bytes to halfwords, top",
Word: 0x65083c00, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBF2CVT; inst_gen.go + arm64sveenc.s"},
{Name: "ZBF2CVTLT", Summary: "Convert BFloat16 pairs from bytes to halfwords, top, no rounding",
Word: 0x65093c00, Form: ExtFormZUnpack, Arr: ExtArrH, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBF2CVTLT; inst_gen.go + arm64sveenc.s"},
{Name: "ZBFADD", Summary: "Add BFloat16 halfwords, merging",
Word: 0x65008000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBFADD; inst_gen.go + arm64sveenc.s"},
{Name: "ZBFADD", Summary: "Add BFloat16 halfwords, unpredicated",
Word: 0x65000000, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBFADD; inst_gen.go + arm64sveenc.s"},
{Name: "ZBFCLAMP", Summary: "Clamp BFloat16 halfwords between bounds, unpredicated",
Word: 0x64202400, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBFCLAMP; inst_gen.go + arm64sveenc.s"},
{Name: "ZBFMAX", Summary: "Maximum of BFloat16 halfwords, merging",
Word: 0x65068000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBFMAX; inst_gen.go + arm64sveenc.s"},
{Name: "ZBFMAXNM", Summary: "Maximum number of BFloat16 halfwords, merging",
Word: 0x65048000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBFMAXNM; inst_gen.go + arm64sveenc.s"},
{Name: "ZBFMIN", Summary: "Minimum of BFloat16 halfwords, merging",
Word: 0x65078000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBFMIN; inst_gen.go + arm64sveenc.s"},
{Name: "ZBFMINNM", Summary: "Minimum number of BFloat16 halfwords, merging",
Word: 0x65058000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBFMINNM; inst_gen.go + arm64sveenc.s"},
{Name: "ZBFMUL", Summary: "Multiply BFloat16 halfwords, merging",
Word: 0x65028000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBFMUL; inst_gen.go + arm64sveenc.s"},
{Name: "ZBFMUL", Summary: "Multiply BFloat16 halfwords, unpredicated",
Word: 0x65000800, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBFMUL; inst_gen.go + arm64sveenc.s"},
{Name: "ZBFSUB", Summary: "Subtract BFloat16 halfwords, merging",
Word: 0x65018000, Form: ExtFormZPredicatedSource, Arr: ExtArrH, PgQual: ExtQualMerging, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBFSUB; inst_gen.go + arm64sveenc.s"},
{Name: "ZBFSUB", Summary: "Subtract BFloat16 halfwords, unpredicated",
Word: 0x65000400, Form: ExtFormVectorsZm, Arr: ExtArrH, Feature: ExtFeatureSVE2,
Ref: "ARM DDI 0487J SVE2: ZBFSUB; inst_gen.go + arm64sveenc.s"},
// --- the SVE2 crypto family ----------------------------------------------
//
// The multi-precision carry steps (ADCLB, ADCLT, SBCLB, SBCLT), the SHA3