feat(asm): the immediate multiply and arm64 indirect branches GOROOT writes
Assisted-by: GLM 5.3 Flash
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@@ -637,6 +637,20 @@ func encodeARM64Branch(mnem string, ops []*ast.Operand, pc int, offsets map[stri
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return a64wordLE(a64UncondBranch(opc, uint32(rn), 0)), nil
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}
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// The bare spelling BL R9 is the same indirect branch: the parser reads
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// a bare identifier as a symbol, and one named for a register is an
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// indirect branch through it, which the toolchain accepts alongside the
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// parenthesised form (BL (R3) and BL R3 both encode BLR R3).
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if op.Addr.Sym != nil && op.Addr.Sym.Pseudo == "" && op.Addr.Base == "" && op.Addr.Index == "" {
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if rn := arm64RegNum(op.Addr.Sym.Name); rn >= 0 {
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opc := uint32(0) // BR
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if link {
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opc = 1 // BLR
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}
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return a64wordLE(a64UncondBranch(opc, uint32(rn), 0)), nil
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}
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}
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// Symbol reference: BL sym(SB), or B sym(SB) for a tail call, against a
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// relocation (R_CALLARM64 either way).
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if op.Addr.Sym != nil && op.Addr.Sym.Pseudo == "SB" {
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@@ -1454,6 +1468,15 @@ func encodeARM64Mov(instr *ast.Instr, mnem string, wb string, fi arm64FrameInfo,
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}
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return encodeARM64SBAddr(src.Imm.Sym, rd, relocs), nil
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}
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// Immediate → memory: only storing zero is encodable (the ZR
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// register); the toolchain rejects any other immediate-to-memory
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// combination ("illegal combination").
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if isMemOperand(dst) {
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if arm64Imm64(src) != 0 {
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return nil, fmt.Errorf("%s: illegal combination: an immediate store must be zero", mnem)
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}
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return encodeARM64MemOp(mnem, dst, 31, false, fi, "")
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}
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rd := arm64RegNum(operandRegName(dst))
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if rd < 0 {
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return nil, fmt.Errorf("%s $imm: invalid destination register", mnem)
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+36
-20
@@ -640,7 +640,16 @@ func (e *enc) encodeDoubleShift(base string, ops []Operand, size int) error {
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func (e *enc) encodeImul(ops []Operand, size int) error {
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switch len(ops) {
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case 2:
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// IMUL r, r/m: 0x0F 0xAF.
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// Two shapes. The leading-immediate spelling IMUL $imm, r multiplies
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// r in place (dst = rm = r): the shape GOROOT's clock code writes.
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// Otherwise IMUL r, r/m: 0x0F 0xAF.
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if imm, ok := ops[0].(Imm); ok {
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dstReg, isReg := ops[1].(Reg)
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if !isReg {
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return fmt.Errorf("IMUL: destination must be a register")
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}
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return e.encodeImulImm(imm, dstReg, dstReg, size)
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}
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dstReg, ok := ops[1].(Reg)
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if !ok {
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return fmt.Errorf("IMUL: destination must be a register")
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@@ -660,29 +669,36 @@ func (e *enc) encodeImul(ops []Operand, size int) error {
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if !ok {
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return fmt.Errorf("IMUL: immediate operand expected first")
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}
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// Plan 9 order: IMUL $imm, src, dst.
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if fits8(int64(imm)) {
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i := newInstr(size, []byte{0x6B})
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if err := setRM(i, dstReg, ops[1], size); err != nil {
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return err
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}
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i.imm = []byte{byte(int8(imm))}
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return e.emit(i)
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}
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i := newInstr(size, []byte{0x69})
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if err := setRM(i, dstReg, ops[1], size); err != nil {
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return err
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}
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immBytes, err := immediate(int64(imm), size, false)
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if err != nil {
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return err
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}
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i.imm = immBytes
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return e.emit(i)
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// Plan 9 order: IMUL $imm, src, dst; the source stays a general
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// r/m operand (setRM takes registers and memory alike).
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return e.encodeImulImm(imm, ops[1], dstReg, size)
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}
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return fmt.Errorf("IMUL expects 2 or 3 operands, got %d", len(ops))
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}
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// encodeImulImm emits the immediate multiply: 0x6B with a sign-extended imm8
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// when the value fits, 0x69 with a 32-bit immediate otherwise.
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func (e *enc) encodeImulImm(imm Imm, rm Operand, dst Reg, size int) error {
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if fits8(int64(imm)) {
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i := newInstr(size, []byte{0x6B})
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if err := setRM(i, dst, rm, size); err != nil {
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return err
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}
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i.imm = []byte{byte(int8(imm))}
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return e.emit(i)
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}
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i := newInstr(size, []byte{0x69})
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if err := setRM(i, dst, rm, size); err != nil {
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return err
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}
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immBytes, err := immediate(int64(imm), size, false)
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if err != nil {
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return err
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}
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i.imm = immBytes
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return e.emit(i)
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}
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// --- PUSH / POP -------------------------------------------------------------
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func (e *enc) encodePushPop(ops []Operand, size int, push bool) error {
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