From 863926abd62c895cb08597885a2993eaeb568597 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20Balv=C3=ADn?= Date: Sun, 20 Sep 2026 19:15:05 +0200 Subject: [PATCH] test(verify): register the loong64 vector kernels Assisted-by: GLM 5.3 Flash --- verify/l64_groundtruth_test.go | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/verify/l64_groundtruth_test.go b/verify/l64_groundtruth_test.go index 571cad1..5ff8897 100644 --- a/verify/l64_groundtruth_test.go +++ b/verify/l64_groundtruth_test.go @@ -31,6 +31,25 @@ func TestGroundTruthLOONG64(t *testing.T) { "../testdata/verify/vector_loong64.s", "../testdata/verify/pcalign_loong64.s", "../testdata/verify/l64forms_loong64.s", + "../testdata/verify/vector_arith_add_loong64.s", + "../testdata/verify/vector_arith_sub_loong64.s", + "../testdata/verify/vector_arith_sat_loong64.s", + "../testdata/verify/vector_logic_loong64.s", + "../testdata/verify/vector_madd_loong64.s", + "../testdata/verify/vector_maddwiden_loong64.s", + "../testdata/verify/vector_mul_loong64.s", + "../testdata/verify/vector_mulwiden_loong64.s", + "../testdata/verify/vector_msub_loong64.s", + "../testdata/verify/vector_divmod_loong64.s", + "../testdata/verify/vector_shift_loong64.s", + "../testdata/verify/vector_bitops_loong64.s", + "../testdata/verify/vector_interleave_loong64.s", + "../testdata/verify/vector_unary_loong64.s", + "../testdata/verify/vector_shuffle_loong64.s", + "../testdata/verify/vector_fp_loong64.s", + "../testdata/verify/vector_bounds_loong64.s", + "../testdata/verify/amdb_loong64.s", + "../testdata/verify/pseudos_loong64.s", "trampoline_loong64.s", } { t.Run(path, func(t *testing.T) {