feat(arch): add the amd64 fp16 packed conversion family
Assisted-by: GLM 5.3
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@@ -660,6 +660,396 @@ var amd64GoldenRows = []amd64GoldenRow{
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{"vcvtusi2sh rd-sae, 64-bit, high registers", "VCVTUSI2SH",
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[]ExtOperand{ExtXmm(29), ExtGpr64(12), ExtRounded(ExtXmm(30), ExtRoundDown)},
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"624596307bf4", "62 45 96 30 7b f4 vcvtusi2sh %r12,{rd-sae},%xmm29,%xmm30"},
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// The FP16 packed conversions, the fourteen directions between the FP16
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// lanes and the integer and double-precision companions. The register
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// rows and the rounding rows are quoted from the local GNU assembler's
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// output; the memory rows follow the listing's full-width and broadcast
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// spellings, whose source displacements are N times the plain SDM
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// displacement the disp8 bytes carry under the assembler's compressed
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// displacement scaling, and the rows with no GNU line are derived: the
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// plain full-width load of a narrowing convert the AT&T syntax cannot
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// spell without a size hint, laid out by the broadcast row minus EVEX.b.
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{"vcvtph2w zmm", "VCVTPH2W",
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[]ExtOperand{ExtZmm(5), ExtZmm(6)},
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"62f57d487df5", "62 f5 7d 48 7d f5 vcvtph2w %zmm5,%zmm6"},
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{"vcvtph2w ymm", "VCVTPH2W",
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[]ExtOperand{ExtYmm(5), ExtYmm(6)},
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"62f57d287df5", "62 f5 7d 28 7d f5 vcvtph2w %ymm5,%ymm6"},
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{"vcvtph2w xmm", "VCVTPH2W",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f57d087df5", "62 f5 7d 08 7d f5 vcvtph2w %xmm5,%xmm6"},
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{"vcvtph2uw zmm", "VCVTPH2UW",
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[]ExtOperand{ExtZmm(5), ExtZmm(6)},
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"62f57c487df5", "62 f5 7c 48 7d f5 vcvtph2uw %zmm5,%zmm6"},
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{"vcvtph2uw ymm", "VCVTPH2UW",
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[]ExtOperand{ExtYmm(5), ExtYmm(6)},
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"62f57c287df5", "62 f5 7c 28 7d f5 vcvtph2uw %ymm5,%ymm6"},
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{"vcvtph2uw xmm", "VCVTPH2UW",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f57c087df5", "62 f5 7c 08 7d f5 vcvtph2uw %xmm5,%xmm6"},
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{"vcvtw2ph zmm", "VCVTW2PH",
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[]ExtOperand{ExtZmm(5), ExtZmm(6)},
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"62f57e487df5", "62 f5 7e 48 7d f5 vcvtw2ph %zmm5,%zmm6"},
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{"vcvtw2ph ymm", "VCVTW2PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(6)},
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"62f57e287df5", "62 f5 7e 28 7d f5 vcvtw2ph %ymm5,%ymm6"},
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{"vcvtw2ph xmm", "VCVTW2PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f57e087df5", "62 f5 7e 08 7d f5 vcvtw2ph %xmm5,%xmm6"},
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{"vcvtuw2ph zmm", "VCVTUW2PH",
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[]ExtOperand{ExtZmm(5), ExtZmm(6)},
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"62f57f487df5", "62 f5 7f 48 7d f5 vcvtuw2ph %zmm5,%zmm6"},
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{"vcvtuw2ph ymm", "VCVTUW2PH",
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[]ExtOperand{ExtYmm(5), ExtYmm(6)},
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"62f57f287df5", "62 f5 7f 28 7d f5 vcvtuw2ph %ymm5,%ymm6"},
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{"vcvtuw2ph xmm", "VCVTUW2PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f57f087df5", "62 f5 7f 08 7d f5 vcvtuw2ph %xmm5,%xmm6"},
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{"vcvtph2dq zmm", "VCVTPH2DQ",
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[]ExtOperand{ExtYmm(5), ExtZmm(6)},
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"62f57d485bf5", "62 f5 7d 48 5b f5 vcvtph2dq %ymm5,%zmm6"},
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{"vcvtph2dq ymm", "VCVTPH2DQ",
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[]ExtOperand{ExtXmm(5), ExtYmm(6)},
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"62f57d285bf5", "62 f5 7d 28 5b f5 vcvtph2dq %xmm5,%ymm6"},
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{"vcvtph2dq xmm", "VCVTPH2DQ",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f57d085bf5", "62 f5 7d 08 5b f5 vcvtph2dq %xmm5,%xmm6"},
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{"vcvtph2udq zmm", "VCVTPH2UDQ",
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[]ExtOperand{ExtYmm(5), ExtZmm(6)},
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"62f57c4879f5", "62 f5 7c 48 79 f5 vcvtph2udq %ymm5,%zmm6"},
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{"vcvtph2udq ymm", "VCVTPH2UDQ",
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[]ExtOperand{ExtXmm(5), ExtYmm(6)},
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"62f57c2879f5", "62 f5 7c 28 79 f5 vcvtph2udq %xmm5,%ymm6"},
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{"vcvtph2udq xmm", "VCVTPH2UDQ",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f57c0879f5", "62 f5 7c 08 79 f5 vcvtph2udq %xmm5,%xmm6"},
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{"vcvtdq2ph zmm to ymm", "VCVTDQ2PH",
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[]ExtOperand{ExtZmm(5), ExtYmm(6)},
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"62f57c485bf5", "62 f5 7c 48 5b f5 vcvtdq2ph %zmm5,%ymm6"},
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{"vcvtdq2ph ymm to xmm", "VCVTDQ2PH",
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[]ExtOperand{ExtYmm(5), ExtXmm(6)},
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"62f57c285bf5", "62 f5 7c 28 5b f5 vcvtdq2ph %ymm5,%xmm6"},
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{"vcvtdq2ph xmm to xmm", "VCVTDQ2PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f57c085bf5", "62 f5 7c 08 5b f5 vcvtdq2ph %xmm5,%xmm6"},
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{"vcvtudq2ph zmm to ymm", "VCVTUDQ2PH",
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[]ExtOperand{ExtZmm(5), ExtYmm(6)},
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"62f57f487af5", "62 f5 7f 48 7a f5 vcvtudq2ph %zmm5,%ymm6"},
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{"vcvtudq2ph ymm to xmm", "VCVTUDQ2PH",
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[]ExtOperand{ExtYmm(5), ExtXmm(6)},
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"62f57f287af5", "62 f5 7f 28 7a f5 vcvtudq2ph %ymm5,%xmm6"},
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{"vcvtudq2ph xmm to xmm", "VCVTUDQ2PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f57f087af5", "62 f5 7f 08 7a f5 vcvtudq2ph %xmm5,%xmm6"},
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{"vcvtph2qq zmm", "VCVTPH2QQ",
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[]ExtOperand{ExtXmm(5), ExtZmm(6)},
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"62f57d487bf5", "62 f5 7d 48 7b f5 vcvtph2qq %xmm5,%zmm6"},
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{"vcvtph2qq ymm", "VCVTPH2QQ",
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[]ExtOperand{ExtXmm(5), ExtYmm(6)},
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"62f57d287bf5", "62 f5 7d 28 7b f5 vcvtph2qq %xmm5,%ymm6"},
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{"vcvtph2qq xmm", "VCVTPH2QQ",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f57d087bf5", "62 f5 7d 08 7b f5 vcvtph2qq %xmm5,%xmm6"},
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{"vcvtph2uqq zmm", "VCVTPH2UQQ",
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[]ExtOperand{ExtXmm(5), ExtZmm(6)},
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"62f57d4879f5", "62 f5 7d 48 79 f5 vcvtph2uqq %xmm5,%zmm6"},
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{"vcvtph2uqq ymm", "VCVTPH2UQQ",
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[]ExtOperand{ExtXmm(5), ExtYmm(6)},
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"62f57d2879f5", "62 f5 7d 28 79 f5 vcvtph2uqq %xmm5,%ymm6"},
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{"vcvtph2uqq xmm", "VCVTPH2UQQ",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f57d0879f5", "62 f5 7d 08 79 f5 vcvtph2uqq %xmm5,%xmm6"},
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{"vcvtqq2ph zmm to xmm", "VCVTQQ2PH",
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[]ExtOperand{ExtZmm(5), ExtXmm(6)},
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"62f5fc485bf5", "62 f5 fc 48 5b f5 vcvtqq2ph %zmm5,%xmm6"},
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{"vcvtqq2ph ymm to xmm", "VCVTQQ2PH",
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[]ExtOperand{ExtYmm(5), ExtXmm(6)},
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"62f5fc285bf5", "62 f5 fc 28 5b f5 vcvtqq2ph %ymm5,%xmm6"},
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{"vcvtqq2ph xmm to xmm", "VCVTQQ2PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f5fc085bf5", "62 f5 fc 08 5b f5 vcvtqq2ph %xmm5,%xmm6"},
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{"vcvtuqq2ph zmm to xmm", "VCVTUQQ2PH",
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[]ExtOperand{ExtZmm(5), ExtXmm(6)},
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"62f5ff487af5", "62 f5 ff 48 7a f5 vcvtuqq2ph %zmm5,%xmm6"},
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{"vcvtuqq2ph ymm to xmm", "VCVTUQQ2PH",
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[]ExtOperand{ExtYmm(5), ExtXmm(6)},
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"62f5ff287af5", "62 f5 ff 28 7a f5 vcvtuqq2ph %ymm5,%xmm6"},
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{"vcvtuqq2ph xmm to xmm", "VCVTUQQ2PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f5ff087af5", "62 f5 ff 08 7a f5 vcvtuqq2ph %xmm5,%xmm6"},
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{"vcvtph2pd zmm", "VCVTPH2PD",
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[]ExtOperand{ExtXmm(5), ExtZmm(6)},
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"62f57c485af5", "62 f5 7c 48 5a f5 vcvtph2pd %xmm5,%zmm6"},
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{"vcvtph2pd ymm", "VCVTPH2PD",
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[]ExtOperand{ExtXmm(5), ExtYmm(6)},
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"62f57c285af5", "62 f5 7c 28 5a f5 vcvtph2pd %xmm5,%ymm6"},
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{"vcvtph2pd xmm", "VCVTPH2PD",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f57c085af5", "62 f5 7c 08 5a f5 vcvtph2pd %xmm5,%xmm6"},
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{"vcvtpd2ph zmm to xmm", "VCVTPD2PH",
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[]ExtOperand{ExtZmm(5), ExtXmm(6)},
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"62f5fd485af5", "62 f5 fd 48 5a f5 vcvtpd2ph %zmm5,%xmm6"},
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{"vcvtpd2ph ymm to xmm", "VCVTPD2PH",
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[]ExtOperand{ExtYmm(5), ExtXmm(6)},
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"62f5fd285af5", "62 f5 fd 28 5a f5 vcvtpd2ph %ymm5,%xmm6"},
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{"vcvtpd2ph xmm to xmm", "VCVTPD2PH",
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[]ExtOperand{ExtXmm(5), ExtXmm(6)},
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"62f5fd085af5", "62 f5 fd 08 5a f5 vcvtpd2ph %xmm5,%xmm6"},
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// The rounding rows of the converting directions: the FP16-to-integer
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// and the integer-to-FP16 conversions round and take EVEX.RC on their
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// 512-bit register forms, exactly as the arithmetic does, and VCVTPH2PD,
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// which widens exactly, takes none.
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{"vcvtph2w rn-sae", "VCVTPH2W",
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[]ExtOperand{ExtZmm(5), ExtRounded(ExtZmm(6), ExtRoundNearest)},
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"62f57d187df5", "62 f5 7d 18 7d f5 vcvtph2w {rn-sae},%zmm5,%zmm6"},
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{"vcvtph2uw rz-sae", "VCVTPH2UW",
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[]ExtOperand{ExtZmm(5), ExtRounded(ExtZmm(6), ExtRoundTruncate)},
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"62f57c787df5", "62 f5 7c 78 7d f5 vcvtph2uw {rz-sae},%zmm5,%zmm6"},
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{"vcvtph2dq rn-sae", "VCVTPH2DQ",
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[]ExtOperand{ExtYmm(5), ExtRounded(ExtZmm(6), ExtRoundNearest)},
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"62f57d185bf5", "62 f5 7d 18 5b f5 vcvtph2dq {rn-sae},%ymm5,%zmm6"},
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{"vcvtph2udq rn-sae", "VCVTPH2UDQ",
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[]ExtOperand{ExtYmm(5), ExtRounded(ExtZmm(6), ExtRoundNearest)},
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"62f57c1879f5", "62 f5 7c 18 79 f5 vcvtph2udq {rn-sae},%ymm5,%zmm6"},
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{"vcvtph2qq rz-sae", "VCVTPH2QQ",
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[]ExtOperand{ExtXmm(5), ExtRounded(ExtZmm(6), ExtRoundTruncate)},
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"62f57d787bf5", "62 f5 7d 78 7b f5 vcvtph2qq {rz-sae},%xmm5,%zmm6"},
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{"vcvtph2uqq rz-sae", "VCVTPH2UQQ",
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[]ExtOperand{ExtXmm(5), ExtRounded(ExtZmm(6), ExtRoundTruncate)},
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"62f57d7879f5", "62 f5 7d 78 79 f5 vcvtph2uqq {rz-sae},%xmm5,%zmm6"},
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{"vcvtw2ph rz-sae", "VCVTW2PH",
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[]ExtOperand{ExtZmm(5), ExtRounded(ExtZmm(6), ExtRoundTruncate)},
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"62f57e787df5", "62 f5 7e 78 7d f5 vcvtw2ph {rz-sae},%zmm5,%zmm6"},
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{"vcvtuw2ph rn-sae", "VCVTUW2PH",
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[]ExtOperand{ExtZmm(5), ExtRounded(ExtZmm(6), ExtRoundNearest)},
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"62f57f187df5", "62 f5 7f 18 7d f5 vcvtuw2ph {rn-sae},%zmm5,%zmm6"},
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{"vcvtdq2ph rn-sae", "VCVTDQ2PH",
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[]ExtOperand{ExtZmm(5), ExtRounded(ExtYmm(6), ExtRoundNearest)},
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"62f57c185bf5", "62 f5 7c 18 5b f5 vcvtdq2ph {rn-sae},%zmm5,%ymm6"},
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{"vcvtudq2ph ru-sae", "VCVTUDQ2PH",
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[]ExtOperand{ExtZmm(5), ExtRounded(ExtYmm(6), ExtRoundUp)},
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"62f57f587af5", "62 f5 7f 58 7a f5 vcvtudq2ph {ru-sae},%zmm5,%ymm6"},
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{"vcvtqq2ph rz-sae", "VCVTQQ2PH",
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[]ExtOperand{ExtZmm(5), ExtRounded(ExtXmm(6), ExtRoundTruncate)},
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"62f5fc785bf5", "62 f5 fc 78 5b f5 vcvtqq2ph {rz-sae},%zmm5,%xmm6"},
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{"vcvtuqq2ph rd-sae", "VCVTUQQ2PH",
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[]ExtOperand{ExtZmm(5), ExtRounded(ExtXmm(6), ExtRoundDown)},
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"62f5ff387af5", "62 f5 ff 38 7a f5 vcvtuqq2ph {rd-sae},%zmm5,%xmm6"},
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{"vcvtpd2ph rz-sae", "VCVTPD2PH",
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[]ExtOperand{ExtZmm(5), ExtRounded(ExtXmm(6), ExtRoundTruncate)},
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"62f5fd785af5", "62 f5 fd 78 5a f5 vcvtpd2ph {rz-sae},%zmm5,%xmm6"},
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// High registers across the conversion shapes, exercising every EVEX
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// extension bit: the source above 15 clears B bar and X bar, the
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// destination above 15 R bar.
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{"vcvtph2w, high registers", "VCVTPH2W",
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[]ExtOperand{ExtZmm(28), ExtZmm(29)},
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"62057d487dec", "62 05 7d 48 7d ec vcvtph2w %zmm28,%zmm29"},
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{"vcvtph2dq, high registers", "VCVTPH2DQ",
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[]ExtOperand{ExtYmm(28), ExtZmm(29)},
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"62057d485bec", "62 05 7d 48 5b ec vcvtph2dq %ymm28,%zmm29"},
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{"vcvtdq2ph, high registers", "VCVTDQ2PH",
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[]ExtOperand{ExtZmm(29), ExtYmm(30)},
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"62057c485bf5", "62 05 7c 48 5b f5 vcvtdq2ph %zmm29,%ymm30"},
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{"vcvtph2qq, high registers", "VCVTPH2QQ",
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[]ExtOperand{ExtXmm(28), ExtZmm(29)},
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"62057d487bec", "62 05 7d 48 7b ec vcvtph2qq %xmm28,%zmm29"},
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{"vcvtpd2ph, high registers", "VCVTPD2PH",
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[]ExtOperand{ExtZmm(28), ExtXmm(29)},
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"6205fd485aec", "62 05 fd 48 5a ec vcvtpd2ph %zmm28,%xmm29"},
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// The memory forms of the conversions: the FP16 sources read full-width
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// vectors, the integer sources their elements under the broadcast. The
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// disp8 rows quote the listing's compressed spellings, whose source is N
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// times the plain displacement the bytes carry.
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{"vcvtph2w memory source", "VCVTPH2W",
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[]ExtOperand{ExtMemory(9, 0), ExtZmm(30)},
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"62457d487d31", "62 45 7d 48 7d 31 vcvtph2w (%r9),%zmm30"},
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{"vcvtph2w memory source disp8", "VCVTPH2W",
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[]ExtOperand{ExtMemory(1, 127), ExtZmm(30)},
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"62657d487d717f", "62 65 7d 48 7d 71 7f vcvtph2w 0x1fc0(%rcx),%zmm30 (Disp8(7f))"},
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{"vcvtph2w ymm memory source", "VCVTPH2W",
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[]ExtOperand{ExtMemory(9, 0), ExtYmm(30)},
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"62457d287d31", "62 45 7d 28 7d 31 vcvtph2w (%r9),%ymm30"},
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{"vcvtph2w xmm memory source", "VCVTPH2W",
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[]ExtOperand{ExtMemory(9, 0), ExtXmm(30)},
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"62457d087d31", "62 45 7d 08 7d 31 vcvtph2w (%r9),%xmm30"},
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{"vcvtph2uw memory source", "VCVTPH2UW",
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[]ExtOperand{ExtMemory(9, 0), ExtZmm(30)},
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"62457c487d31", "62 45 7c 48 7d 31 vcvtph2uw (%r9),%zmm30"},
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{"vcvtw2ph memory source", "VCVTW2PH",
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[]ExtOperand{ExtMemory(9, 0), ExtZmm(30)},
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"62457e487d31", "62 45 7e 48 7d 31 vcvtw2ph (%r9),%zmm30"},
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{"vcvtw2ph ymm memory source", "VCVTW2PH",
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[]ExtOperand{ExtMemory(9, 0), ExtYmm(30)},
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"62457e287d31", "62 45 7e 28 7d 31 vcvtw2ph (%r9),%ymm30"},
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{"vcvtph2dq memory source", "VCVTPH2DQ",
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[]ExtOperand{ExtMemory(9, 0), ExtZmm(30)},
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"62457d485b31", "62 45 7d 48 5b 31 vcvtph2dq (%r9),%zmm30"},
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{"vcvtph2dq memory source disp8", "VCVTPH2DQ",
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[]ExtOperand{ExtMemory(1, 127), ExtZmm(30)},
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"62657d485b717f", "62 65 7d 48 5b 71 7f vcvtph2dq 0xfe0(%rcx),%zmm30 (Disp8(7f))"},
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{"vcvtph2dq ymm memory source", "VCVTPH2DQ",
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[]ExtOperand{ExtMemory(9, 0), ExtYmm(30)},
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"62457d285b31", "62 45 7d 28 5b 31 vcvtph2dq (%r9),%ymm30"},
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{"vcvtph2udq memory source", "VCVTPH2UDQ",
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[]ExtOperand{ExtMemory(9, 0), ExtZmm(30)},
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"62457c487931", "62 45 7c 48 79 31 vcvtph2udq (%r9),%zmm30"},
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{"vcvtdq2ph memory source", "VCVTDQ2PH",
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[]ExtOperand{ExtMemory(9, 0), ExtYmm(30)},
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"62457c485b31", "62 45 7c 48 5b 31 vcvtdq2ph (%r9),%ymm30"},
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{"vcvtph2qq memory source", "VCVTPH2QQ",
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[]ExtOperand{ExtMemory(9, 0), ExtZmm(30)},
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"62457d487b31", "62 45 7d 48 7b 31 vcvtph2qq (%r9),%zmm30"},
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{"vcvtph2qq memory source disp8", "VCVTPH2QQ",
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[]ExtOperand{ExtMemory(1, 127), ExtZmm(30)},
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"62657d487b717f", "62 65 7d 48 7b 71 7f vcvtph2qq 0x7f0(%rcx),%zmm30 (Disp8(7f))"},
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{"vcvtph2qq ymm memory source", "VCVTPH2QQ",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtYmm(30)},
|
||||
"62457d287b31", "62 45 7d 28 7b 31 vcvtph2qq (%r9),%ymm30"},
|
||||
{"vcvtph2uqq memory source", "VCVTPH2UQQ",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtZmm(30)},
|
||||
"62457d487931", "62 45 7d 48 79 31 vcvtph2uqq (%r9),%zmm30"},
|
||||
{"vcvtph2pd memory source", "VCVTPH2PD",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtZmm(30)},
|
||||
"62457c485a31", "62 45 7c 48 5a 31 vcvtph2pd (%r9),%zmm30"},
|
||||
{"vcvtph2pd memory source disp8", "VCVTPH2PD",
|
||||
[]ExtOperand{ExtMemory(1, 127), ExtZmm(30)},
|
||||
"62657c485a717f", "62 65 7c 48 5a 71 7f vcvtph2pd 0x7f0(%rcx),%zmm30 (Disp8(7f))"},
|
||||
{"vcvtph2pd ymm memory source", "VCVTPH2PD",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtYmm(30)},
|
||||
"62457c285a31", "62 45 7c 28 5a 31 vcvtph2pd (%r9),%ymm30"},
|
||||
{"vcvtqq2ph plain memory source", "VCVTQQ2PH",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtXmm(30)},
|
||||
"6245fc485b31", ""},
|
||||
{"vcvtuqq2ph plain memory source", "VCVTUQQ2PH",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtXmm(30)},
|
||||
"6245ff487a31", ""},
|
||||
{"vcvtpd2ph plain memory source", "VCVTPD2PH",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtXmm(30)},
|
||||
"6245fd485a31", ""},
|
||||
|
||||
// The broadcast forms of the converting sources: a single element the
|
||||
// hardware splats across the lanes, one word, dword or qword as the
|
||||
// direction's input element spells it.
|
||||
{"vcvtw2ph broadcast source", "VCVTW2PH",
|
||||
[]ExtOperand{ExtBroadcast(9, 0), ExtZmm(30)},
|
||||
"62457e587d31", "62 45 7e 58 7d 31 vcvtw2ph (%r9){1to32},%zmm30"},
|
||||
{"vcvtw2ph broadcast source disp8", "VCVTW2PH",
|
||||
[]ExtOperand{ExtBroadcast(1, 127), ExtZmm(30)},
|
||||
"62657e587d717f", "62 65 7e 58 7d 71 7f vcvtw2ph 0xfe(%rcx){1to32},%zmm30 (Disp8(7f))"},
|
||||
{"vcvtuw2ph broadcast source", "VCVTUW2PH",
|
||||
[]ExtOperand{ExtBroadcast(9, 0), ExtZmm(30)},
|
||||
"62457f587d31", "62 45 7f 58 7d 31 vcvtuw2ph (%r9){1to32},%zmm30"},
|
||||
{"vcvtuw2ph broadcast source disp8", "VCVTUW2PH",
|
||||
[]ExtOperand{ExtBroadcast(1, 127), ExtZmm(30)},
|
||||
"62657f587d717f", "62 65 7f 58 7d 71 7f vcvtuw2ph 0xfe(%rcx){1to32},%zmm30 (Disp8(7f))"},
|
||||
{"vcvtdq2ph broadcast source", "VCVTDQ2PH",
|
||||
[]ExtOperand{ExtBroadcast(9, 0), ExtYmm(30)},
|
||||
"62457c585b31", "62 45 7c 58 5b 31 vcvtdq2ph (%r9){1to16},%ymm30"},
|
||||
{"vcvtdq2ph broadcast source disp8", "VCVTDQ2PH",
|
||||
[]ExtOperand{ExtBroadcast(1, 127), ExtYmm(30)},
|
||||
"62657c585b717f", "62 65 7c 58 5b 71 7f vcvtdq2ph 0x1fc(%rcx){1to16},%ymm30 (Disp8(7f))"},
|
||||
{"vcvtudq2ph broadcast source", "VCVTUDQ2PH",
|
||||
[]ExtOperand{ExtBroadcast(9, 0), ExtYmm(30)},
|
||||
"62457f587a31", "62 45 7f 58 7a 31 vcvtudq2ph (%r9){1to16},%ymm30"},
|
||||
{"vcvtudq2ph broadcast source disp8", "VCVTUDQ2PH",
|
||||
[]ExtOperand{ExtBroadcast(1, 127), ExtYmm(30)},
|
||||
"62657f587a717f", "62 65 7f 58 7a 71 7f vcvtudq2ph 0x1fc(%rcx){1to16},%ymm30 (Disp8(7f))"},
|
||||
{"vcvtqq2ph broadcast source", "VCVTQQ2PH",
|
||||
[]ExtOperand{ExtBroadcast(9, 0), ExtXmm(30)},
|
||||
"6245fc585b31", "62 45 fc 58 5b 31 vcvtqq2ph (%r9){1to8},%xmm30"},
|
||||
{"vcvtqq2ph broadcast source disp8", "VCVTQQ2PH",
|
||||
[]ExtOperand{ExtBroadcast(1, 127), ExtXmm(30)},
|
||||
"6265fc585b717f", "62 65 fc 58 5b 71 7f vcvtqq2ph 0x3f8(%rcx){1to8},%xmm30 (Disp8(7f))"},
|
||||
// The 256-bit broadcast row shares the 512-bit row's operand list, both
|
||||
// destinations being XMM, so the resolver cannot tell them apart; the
|
||||
// register row above pins the 256-bit template alone.
|
||||
{"vcvtuqq2ph broadcast source", "VCVTUQQ2PH",
|
||||
[]ExtOperand{ExtBroadcast(9, 0), ExtXmm(30)},
|
||||
"6245ff587a31", "62 45 ff 58 7a 31 vcvtuqq2ph (%r9){1to8},%xmm30"},
|
||||
{"vcvtuqq2ph broadcast source disp8", "VCVTUQQ2PH",
|
||||
[]ExtOperand{ExtBroadcast(1, 127), ExtXmm(30)},
|
||||
"6265ff587a717f", "62 65 ff 58 7a 71 7f vcvtuqq2ph 0x3f8(%rcx){1to8},%xmm30 (Disp8(7f))"},
|
||||
{"vcvtpd2ph broadcast source", "VCVTPD2PH",
|
||||
[]ExtOperand{ExtBroadcast(9, 0), ExtXmm(30)},
|
||||
"6245fd585a31", "62 45 fd 58 5a 31 vcvtpd2ph (%r9){1to8},%xmm30"},
|
||||
{"vcvtpd2ph broadcast source disp8", "VCVTPD2PH",
|
||||
[]ExtOperand{ExtBroadcast(1, 127), ExtXmm(30)},
|
||||
"6265fd585a717f", "62 65 fd 58 5a 71 7f vcvtpd2ph 0x3f8(%rcx){1to8},%xmm30 (Disp8(7f))"},
|
||||
// The 256-bit broadcast row shares the 512-bit row's operand list, both
|
||||
// destinations being XMM, so the resolver cannot tell them apart; the
|
||||
// register row above pins the 256-bit template alone.
|
||||
|
||||
// The write mask over the converting destinations, and one composed
|
||||
// row: the broadcast, the mask and the zeroing on the one word.
|
||||
{"vcvtph2w k7 zeroing", "VCVTPH2W",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtWriteMasked(ExtZmm(30), 7, true)},
|
||||
"62457dcf7d31", "62 45 7d cf 7d 31 vcvtph2w (%r9),%zmm30{%k7}{z}"},
|
||||
{"vcvtph2dq k7 zeroing, memory source", "VCVTPH2DQ",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtWriteMasked(ExtZmm(30), 7, true)},
|
||||
"62457dcf5b31", "62 45 7d cf 5b 31 vcvtph2dq (%r9),%zmm30{%k7}{z}"},
|
||||
{"vcvtph2qq k7, memory source", "VCVTPH2QQ",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtWriteMasked(ExtZmm(30), 7, false)},
|
||||
"62457d4f7b31", "62 45 7d 4f 7b 31 vcvtph2qq (%r9),%zmm30{%k7}"},
|
||||
{"vcvtph2pd k7, memory source", "VCVTPH2PD",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtWriteMasked(ExtZmm(30), 7, false)},
|
||||
"62457c4f5a31", "62 45 7c 4f 5a 31 vcvtph2pd (%r9),%zmm30{%k7}"},
|
||||
{"vcvtw2ph k7 zeroing", "VCVTW2PH",
|
||||
[]ExtOperand{ExtZmm(5), ExtWriteMasked(ExtZmm(6), 7, true)},
|
||||
"62f57ecf7df5", "62 f5 7e cf 7d f5 vcvtw2ph %zmm5,%zmm6{%k7}{z}"},
|
||||
{"vcvtdq2ph k7 zeroing", "VCVTDQ2PH",
|
||||
[]ExtOperand{ExtZmm(5), ExtWriteMasked(ExtYmm(6), 7, true)},
|
||||
"62f57ccf5bf5", "62 f5 7c cf 5b f5 vcvtdq2ph %zmm5,%ymm6{%k7}{z}"},
|
||||
{"vcvtw2ph broadcast under k7 zeroing", "VCVTW2PH",
|
||||
[]ExtOperand{ExtBroadcast(9, 0), ExtWriteMasked(ExtZmm(30), 7, true)},
|
||||
"62457edf7d31", "62 45 7e df 7d 31 vcvtw2ph (%r9){1to32},%zmm30{%k7}{z}"},
|
||||
|
||||
// The memory forms of the scalar conversions, the m16, m32 and m64
|
||||
// sources the manual spells beside each register form. The disp8 rows
|
||||
// quote the listing's compressed spellings, whose source is N times the
|
||||
// plain displacement, N the element size.
|
||||
{"vcvtsh2ss memory source", "VCVTSH2SS",
|
||||
[]ExtOperand{ExtXmm(5), ExtMemory(9, 0), ExtXmm(6)},
|
||||
"62d654081331", "62 d6 54 08 13 31 vcvtsh2ss (%r9),%xmm5,%xmm6"},
|
||||
{"vcvtsh2ss memory source disp8", "VCVTSH2SS",
|
||||
[]ExtOperand{ExtXmm(5), ExtMemory(1, 1), ExtXmm(6)},
|
||||
"62f65408137101", "62 f6 54 08 13 71 01 vcvtsh2ss 0x2(%rcx),%xmm5,%xmm6 (Disp8(01))"},
|
||||
{"vcvtsh2sd memory source", "VCVTSH2SD",
|
||||
[]ExtOperand{ExtXmm(5), ExtMemory(9, 0), ExtXmm(6)},
|
||||
"62d556085a31", "62 d5 56 08 5a 31 vcvtsh2sd (%r9),%xmm5,%xmm6"},
|
||||
{"vcvtsh2sd memory source disp8", "VCVTSH2SD",
|
||||
[]ExtOperand{ExtXmm(5), ExtMemory(1, 1), ExtXmm(6)},
|
||||
"62f556085a7101", "62 f5 56 08 5a 71 01 vcvtsh2sd 0x2(%rcx),%xmm5,%xmm6 (Disp8(01))"},
|
||||
{"vcvtss2sh memory source", "VCVTSS2SH",
|
||||
[]ExtOperand{ExtXmm(5), ExtMemory(9, 0), ExtXmm(6)},
|
||||
"62d554081d31", "62 d5 54 08 1d 31 vcvtss2sh (%r9),%xmm5,%xmm6"},
|
||||
{"vcvtss2sh memory source disp8", "VCVTSS2SH",
|
||||
[]ExtOperand{ExtXmm(5), ExtMemory(1, 1), ExtXmm(6)},
|
||||
"62f554081d7101", "62 f5 54 08 1d 71 01 vcvtss2sh 0x4(%rcx),%xmm5,%xmm6 (Disp8(01))"},
|
||||
{"vcvtsd2sh memory source", "VCVTSD2SH",
|
||||
[]ExtOperand{ExtXmm(5), ExtMemory(9, 0), ExtXmm(6)},
|
||||
"62d5d7085a31", "62 d5 d7 08 5a 31 vcvtsd2sh (%r9),%xmm5,%xmm6"},
|
||||
{"vcvtsd2sh memory source disp8", "VCVTSD2SH",
|
||||
[]ExtOperand{ExtXmm(5), ExtMemory(1, 1), ExtXmm(6)},
|
||||
"62f5d7085a7101", "62 f5 d7 08 5a 71 01 vcvtsd2sh 0x8(%rcx),%xmm5,%xmm6 (Disp8(01))"},
|
||||
{"vcvtsh2si memory source", "VCVTSH2SI",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtGpr32(0)},
|
||||
"62d57e082d01", "62 d5 7e 08 2d 01 vcvtsh2si (%r9),%eax"},
|
||||
{"vcvtsh2si 64-bit memory source", "VCVTSH2SI",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtGpr64(12)},
|
||||
"6255fe082d21", "62 55 fe 08 2d 21 vcvtsh2si (%r9),%r12"},
|
||||
{"vcvtsh2si memory source disp8", "VCVTSH2SI",
|
||||
[]ExtOperand{ExtMemory(1, 1), ExtGpr32(0)},
|
||||
"62f57e082d4101", "62 f5 7e 08 2d 41 01 vcvtsh2si 0x2(%rcx),%eax (Disp8(01))"},
|
||||
{"vcvtsh2usi memory source", "VCVTSH2USI",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtGpr32(0)},
|
||||
"62d57e087901", "62 d5 7e 08 79 01 vcvtsh2usi (%r9),%eax"},
|
||||
{"vcvtsh2usi 64-bit memory source disp8", "VCVTSH2USI",
|
||||
[]ExtOperand{ExtMemory(1, 1), ExtGpr64(12)},
|
||||
"6275fe08796101", "62 75 fe 08 79 61 01 vcvtsh2usi 0x2(%rcx),%r12 (Disp8(01))"},
|
||||
}
|
||||
|
||||
// amd64ResolveEntry finds the table entry a golden row exercises: the entry
|
||||
@@ -951,6 +1341,12 @@ func TestAmd64ExtRejects(t *testing.T) {
|
||||
{"rounding over a memory source", "VADDSH",
|
||||
[]ExtOperand{ExtXmm(29), ExtMemory(9, 0), ExtRounded(ExtXmm(30), ExtRoundNearest)},
|
||||
"the memory form takes no rounding control"},
|
||||
{"rounding over the scalar convert's memory source", "VCVTSS2SH",
|
||||
[]ExtOperand{ExtXmm(5), ExtMemory(9, 0), ExtRounded(ExtXmm(6), ExtRoundNearest)},
|
||||
"the memory form takes no rounding control"},
|
||||
{"rounding beside the converting memory source", "VCVTW2PH",
|
||||
[]ExtOperand{ExtMemory(9, 0), ExtRounded(ExtZmm(30), ExtRoundNearest)},
|
||||
"the memory form takes no rounding control"},
|
||||
{"rounding on a source position", "VADDPH",
|
||||
[]ExtOperand{ExtZmm(5), ExtRounded(ExtZmm(4), ExtRoundUp), ExtZmm(6)},
|
||||
"the position takes none"},
|
||||
@@ -963,6 +1359,21 @@ func TestAmd64ExtRejects(t *testing.T) {
|
||||
{"rounding on an entry without the capability", "VMOVSH",
|
||||
[]ExtOperand{ExtXmm(29), ExtXmm(28), ExtRounded(ExtXmm(30), ExtRoundNearest)},
|
||||
"the entry's destination takes none"},
|
||||
{"rounding on the exactly-widening convert", "VCVTPH2PD",
|
||||
[]ExtOperand{ExtXmm(5), ExtRounded(ExtZmm(6), ExtRoundNearest)},
|
||||
"the entry's destination takes none"},
|
||||
{"wrong source class on the widening convert", "VCVTPH2DQ",
|
||||
[]ExtOperand{ExtZmm(5), ExtZmm(6)},
|
||||
"wants a YMM register"},
|
||||
{"wrong source class on the quarter convert", "VCVTPH2QQ",
|
||||
[]ExtOperand{ExtYmm(5), ExtZmm(6)},
|
||||
"wants an XMM register"},
|
||||
{"wrong destination on the quarter-destination convert", "VCVTQQ2PH",
|
||||
[]ExtOperand{ExtZmm(5), ExtYmm(6)},
|
||||
"wants an XMM register"},
|
||||
{"broadcast on the full-width FP16 source", "VCVTPH2W",
|
||||
[]ExtOperand{ExtBroadcast(9, 0), ExtZmm(30)},
|
||||
"the entry's memory operand takes none"},
|
||||
} {
|
||||
in := amd64ExtInstr(t, tt.mnem, operandClass(t, tt.ops))
|
||||
_, err := in.Encode(tt.ops)
|
||||
@@ -1107,7 +1518,7 @@ func TestAmd64ExtArchBinding(t *testing.T) {
|
||||
t.Errorf("Extensions(%s) carries %d instructions, want none", a, len(got))
|
||||
}
|
||||
}
|
||||
if got := Extensions(AMD64); len(got) != 70 {
|
||||
t.Errorf("the amd64 layer registers %d instructions, want 70", len(got))
|
||||
if got := Extensions(AMD64); len(got) != 112 {
|
||||
t.Errorf("the amd64 layer registers %d instructions, want 112", len(got))
|
||||
}
|
||||
}
|
||||
Reference in new issue
Block a user