From 95025be1bc51e72189d1ec4769f954a779dbea35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20Balv=C3=ADn?= Date: Mon, 21 Sep 2026 19:09:15 +0200 Subject: [PATCH] docs(changelog): describe the encoder entries by content --- CHANGELOG.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index d50976c..fd16b22 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -27,7 +27,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 (`$(32-7)`, `$~63`, `(index*4)(base)`) fold at parse. Expansion happens only on the assembly path: `gasm lint`, `gasm fmt` and the language server keep reading the raw file. -- **The GOROOT instruction wave, part 1.** The encoder now covers the +- **Encoder coverage: the instruction families GOROOT's real code + uses.** The encoder now covers the instruction families GOROOT's real code uses that gasm lacked, byte-verified against `go tool asm`: on amd64 the carry ALU, the atomics (CMPXCHG, XADD, XCHG), AES-NI, SHA-1/256, PCLMULQDQ, CRC32, @@ -43,7 +44,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 Also fixed on the way: arm64 `CASD`/`CASW` lacked an opcode bit, and riscv64 `VSETVLI` with an immediate length now canonicalises to `vsetivli` as the toolchain does. -- **The GOROOT instruction wave, part 2.** The encoder gains the +- **Encoder coverage: quad-register AVX-512 and floating-point + immediates.** The encoder gains the quad-register AVX-512 families (4FMAPS, 4FNMADD, 4VNNIW, VP4DPWSSD, VP4DPWSSDS) with the register list riding the inverted V'VVVV field, floating-point immediates on the SSE scalar moves and arithmetic